Abstract: The operation of grid-connected inverters necessity a
single-phase phase locked loop (PLL) is proposed in this article to
accurately and quickly estimate and detect the grid phase angle. This
article presents the improvement of a method of phase-locked loop.
The novelty is to generate a method (PLL) of synchronizing the grid
with a Notch filter based on adaptive fuzzy logic for inverter systems
connected to the grid. The performance of the proposed method was
tested under normal and abnormal operating conditions (amplitude,
frequency and phase shift variations). In addition, simulation results
with ISPM software are developed to verify the effectiveness of the
proposed method strategy. Finally, the experimental test will be used
to extract the result and discuss the validity of the proposed algorithm.
Abstract: HCV is a hepatotropic RNA virus, transmitted primarily via the blood route, which causes progressive disease such as chronic hepatitis, liver cirrhosis, or hepatocellular carcinoma. HCV nowadays is a global healthcare problem. A variety of immunoassays including old and new technologies are being applied to detect HCV in our country. These methods include Immunochromatography assays (ICA), Fluorescence immunoassay (FIA), Enzyme linked fluorescent assay (ELFA), and Enzyme linked immunosorbent assay (ELISA) to detect HCV antibodies in blood serum, which lately is being slowly replaced by more sensitive methods such as rapid automated analyzer chemiluminescence immunoassay (CLIA). The aim of this study is to estimate HCV infection in carriers and chronic acute patients and to evaluate the use of new diagnostic methods. This study was realized from September 2016 to May 2018. During this study period, 2913 patients were analyzed for the presence of HCV by taking samples from their blood serum. The immunoassays performed were ICA, FIA, ELFA, ELISA, and CLIA assays. Concluding, 82% of patients taken in this study, resulted infected with HCV. Diagnostic methods in clinical laboratories are crucial in the early stages of infection, in the management of chronic hepatitis and in the treatment of patients during their disease.
Abstract: In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.
Abstract: This paper presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.
Abstract: Tissue engineering includes combination of materials and techniques used for the improvement, repair or replacement of the tissue. Scaffolds, permanent or temporally material, are used as support for the creation of the "new cell structures". For this important component (scaffold), a variety of materials can be used. The advantage of some polymeric materials is their cytocompatibility and possibility of biodegradation. Poly(L-lactic acid) (PLLA) is a biodegradable, semi-crystalline thermoplastic polymer. PLLA can be fully degraded into H2O and CO2. In this experiment, the effect of the surface modification of biodegradable polymer (performed by plasma treatment) on the various cell types was studied. The surface parameters and changes of the physicochemical properties of modified PLLA substrates were studied by different methods. Surface wettability was determined by goniometry, surface morphology and roughness study were performed with atomic force microscopy and chemical composition was determined using photoelectron spectroscopy. The physicochemical properties were studied in relation to cytocompatibility of human osteoblast (MG 63 cells), rat vascular smooth muscle cells (VSMC), and human stem cells (ASC) of the adipose tissue in vitro. A fluorescence microscopy was chosen to study and compare cell-material interaction. Important parameters of the cytocompatibility like adhesion, proliferation, viability, shape, spreading of the cells were evaluated. It was found that the modification leads to the change of the surface wettability depending on the time of modification. Short time of exposition (10-120 s) can reduce the wettability of the aged samples, exposition longer than 150 s causes to increase of contact angle of the aged PLLA. The surface morphology is significantly influenced by duration of modification, too. The plasma treatment involves the formation of the crystallites, whose number increases with increasing time of modification. On the basis of physicochemical properties evaluation, the cells were cultivated on the selected samples. Cell-material interactions are strongly affected by material chemical structure and surface morphology. It was proved that the plasma treatment of PLLA has a positive effect on the adhesion, spreading, homogeneity of distribution and viability of all cultivated cells. This effect was even more apparent for the VSMCs and ASCs which homogeneously covered almost the whole surface of the substrate after 7 days of cultivation. The viability of these cells was high (more than 98% for VSMCs, 89-96% for ASCs). This experiment is one part of the basic research, which aims to easily create scaffolds for tissue engineering with subsequent use of stem cells and their subsequent "reorientation" towards the bone cells or smooth muscle cells.
Abstract: In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.
Abstract: The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.
Abstract: Electrospun microtube array membranes (MTAMs) made of PLLA (poly-L-lactic acid) have wide potential applications in tissue engineering. However, their surface hydrophobicity and poor biocompatability have limited their further usage. In this study, the surface of PLLA MTAMs were made hydrophilic by introducing extra functional groups, such as peroxide, via an acetic acid plasma (AAP). UV-graft polymerization of acrylic acid (G-AAc) was then used to produce carboxyl group on MTAMs surface, which bonded covalently with chitosan through EDC / NHS crosslinking agents. To evaluate the effects of the surface modification on PLLA MTAMs, water contact angle (WCA) measurement and cell compatibility tests were carried out. We found that AAP treated electrospun PLLA MTAMs grafted with AAc and, finally, with chitosan immobilized via crosslinking agent, exhibited improved hydrophilic and cell compatibility.
Abstract: This paper presents a model predictive control (MPC)
of a utility interactive three phase inverter (TPI) for a photovoltaic
(PV) system at commercial level. The proposed model uses phase
locked loop (PLL) to synchronize the TPI with the power electric
grid (PEG) and performs MPC control in a dq reference frame. TPI
model consists of a boost converter (BC), maximum power point
tracking (MPPT) control, and a three-leg voltage source inverter
(VSI). The operational model of VSI is used to synthesize the
sinusoidal current and track the reference. The model is validated
using a 35.7 kW PV system in Matlab/Simulink. Implementation
results show simplicity and accuracy, as well as reliability of the
model.
Abstract: This paper describes an optimization tool-based
design strategy for a Current Mode Logic CML divide-by-2 circuit.
Representing a building block for output frequency generation in a
RFID protocol based-frequency synthesizer, the circuit was designed
to minimize the power consumption for driving of multiple loads
with unbalancing (at transceiver level). Implemented with XFAB
XC08 180 nm technology, the circuit was optimized through
MunEDA WiCkeD tool at Cadence Virtuoso Analog Design
Environment ADE.
Abstract: This paper presents a model predictive control (MPC)
of a utility interactive (UI) single phase inverter (SPI) for a
photovoltaic (PV) system at residential/distribution level. The
proposed model uses single-phase phase locked loop (PLL) to
synchronize SPI with the grid and performs MPC control in a dq
reference frame. SPI model consists of boost converter (BC),
maximum power point tracking (MPPT) control, and a full bridge
(FB) voltage source inverter (VSI). No PI regulators to tune and
carrier and modulating waves are required to produce switching
sequence. Instead, the operational model of VSI is used to synthesize
sinusoidal current and track the reference. Model is validated using a
three kW PV system at the input of UI-SPI in Matlab/Simulink.
Implementation and results demonstrate simplicity and accuracy, as
well as reliability of the model.
Abstract: This paper presents a simulation and mathematical model of stand-alone solar-wind-diesel based hybrid energy system (HES). A power management system is designed for multiple energy resources in a stand-alone hybrid energy system. Both Solar photovoltaic and wind energy conversion system consists of maximum power point tracking (MPPT), voltage regulation, and basic power electronic interfaces. An additional diesel generator is included to support and improve the reliability of stand-alone system when renewable energy sources are not available. A power management strategy is introduced to distribute the generated power among resistive load banks. The frequency regulation is developed with conventional phase locked loop (PLL) system. The power management algorithm was applied in Matlab®/Simulink® to simulate the results.
Abstract: A study on the physicochemical properties of Jatropha curcas seed oil for industrial applications were carried out. Physicochemical properties of J. curcas seed oil (59.32% lipids) showed high content of LA (36.70%), iodine value (104.90 mg/g) and saponification value (203.36 mg/g). The present study shows that, J. curcas seed oil is rich in oleic and linoleic acids. The J. curcas seed oil with the highest amount of polyunsaturated fatty acids (linoleic acid) can find an application in surface coating industries and biolubricant base oil applications, whereas the high amount of monounsaturated fatty acid can find an application as a biodiesel feed stock. J. curcas seed oil contains major TAG of monounsaturated OLL, POL, SLL, PLL, OOL, OOO and POP followed by LLL. J. curcas seed oil can be classified as unsaturated oil with an unsaturated fat level of 80.42%. Hence the J. curcas seed oil has great potential for industrial applications such as in paint and surface coatings, production of biodiesel and biolubricant. Therefore, it is crucial to have more research on J. curcas seed oil in the future to explore its potential as a future industrial oilseed crop.
Abstract: This paper presents the 20-GHz fractional PLL (Phase
Locked Loop) circuit for the next generation Wi-Fi by using 90 nm
TSMC process. The newly suggested millimeter wave 16/17
pre-scalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 % of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4-bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4-bit varactor bank. The measured operational bandwidth is 18.2
~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of
-58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
Abstract: This paper presents a method for obtaining the
desired reference current for Voltage Source Converter (VSC) of the Shunt Active Power Filter (SAPF) using Synchronous Reference Frame Theory. The method relies on the performance of the Proportional-Integral (PI) controller for
obtaining the best control performance of the SAPF. To
improve the performance of the PI controller, the feedback
path to the integral term is introduced to compensate the
winding up phenomenon due to integrator. Using Reference
Frame Transformation, reference signals are transformed from
a - b - c stationery frame to 0 - d - q rotating frame.
Using the PI controller, the reference signals in the 0 - d - q rotating frame are controlled to get the desired reference signals for the Pulse Width Modulation. The synchronizer, the Phase Locked Loop (PLL) with PI filter is used for
synchronization, with much emphasis on minimizing delays. The system performance is examined with Shunt Active Power Filter simulation model.
Abstract: The 4G front-end transceiver needs a high
performance which can be obtained mainly with an optimal
architecture and a multi-band Local Oscillator. In this study, we
proposed and presented a new architecture of multi-band frequency
synthesizer based on an Inverse Sine Phase Detector Phase Locked
Loop (ISPD PLL) without any filters and any controlled gain block
and associated with adapted multi band LC tuned VCO using a
several numeric controlled capacitive branches but not binary
weighted. The proposed architecture, based on 0.35μm CMOS
process technology, supporting Multi-band GSM/DCS/DECT/
UMTS/WiMax application and gives a good performances: a phase
noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz -
186dB and a wide band frequency range (from 0.83GHz to 3.5GHz),
that make the proposed architecture amenable for monolithic
integration and 4G multi-band application.
Abstract: This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
Abstract: Phase locked loops in 10 Gb/s and faster data links are
low phase noise devices. Characterization of their phase jitter
transfer functions is difficult because the intrinsic noise of the PLLs
is comparable to the phase noise of the reference clock signal. The
problem is solved by using a linear model to account for the intrinsic
noise. This study also introduces a novel technique for measuring the
transfer function. It involves the use of the reference clock as a
source of wideband excitation, in contrast to the commonly used
sinusoidal excitations at discrete frequencies. The data reported here
include the intrinsic noise of a PLL for 10 Gb/s links and the jitter
transfer function of a PLL for 12.8 Gb/s links. The measured transfer
function suggests that the PLL responded like a second order linear
system to a low noise reference clock.
Abstract: In this paper, we apply the PQ theory with shunt active power filter in an unbalanced and distorted power system voltage to compensate the perturbations generated by non linear load. The power factor is also improved in the current source. The PLL system is used to extract the fundamental component of the even sequence under conditions mentioned of the power system voltage.
Abstract: This paper describes the design of a programmable
FSK-modulator based on VCO and its implementation in 0.35m
CMOS process. The circuit is used to transmit digital data at
100Kbps rate in the frequency range of 400-600MHz. The design
and operation of the modulator is discussed briefly. Further the
characteristics of PLL, frequency synthesizer, VCO and the whole
design are elaborated. The variation among the proposed and tested
specifications is presented. Finally, the layout of sub-modules, pin
configurations, final chip and test results are presented.