Phase Jitter Transfer in High Speed Data Links

Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring the transfer function. It involves the use of the reference clock as a source of wideband excitation, in contrast to the commonly used sinusoidal excitations at discrete frequencies. The data reported here include the intrinsic noise of a PLL for 10 Gb/s links and the jitter transfer function of a PLL for 12.8 Gb/s links. The measured transfer function suggests that the PLL responded like a second order linear system to a low noise reference clock.

Authors:

• Tsunwai Gary Yip

Keywords:

• Intrinsic phase noise
• jitter in data link
• PLL jitter transfer function
• high speed clocking in electronic circuit

References:

[1] Terabyte Bandwidth Initiative, Rambus Developer Forum, Tokyo, Japan,
November 28-29, 2007.
[2] K. Chang, et al., "A 16Gb/s/link, 64GB/s bidirectional asymmetric
memory interface cell," Symposium on VSLI Circuits Digest of
Technical Papers, pp. 126-127, June 2008.
[3] N. Nguyen, et al., "A 16Gb/s Differential I/O Cell with 380fs RJ in an
Emulated 40nm DRAM Process," Symposium on VSLI Circuits Digest
of Technical Papers, pp. 128-129, June 2008.
[4] T. Wu, et al., "Clocking Circuits for a 16Gb/s Memory Interface," IEEE
Custom Integrated Circuits Conference, September 2008.
[5] T.G. Yip et al, "Clock Jitter Reduction in High Speed Interfaces",
Accepted for presentation at DesignCon 2009, Santa Clara, California
USA, February 2009.
[6] Ken Chen et al, "Clock and Circuit Design for a Parallel IO on a First
Generation Cell Processor", Session 28, Paper 28.9, IEEE International
Solid-State Circuit Conference, San Francisco, California, Feb. 6, 2005.