Abstract: Phase locked loops in 10 Gb/s and faster data links are
low phase noise devices. Characterization of their phase jitter
transfer functions is difficult because the intrinsic noise of the PLLs
is comparable to the phase noise of the reference clock signal. The
problem is solved by using a linear model to account for the intrinsic
noise. This study also introduces a novel technique for measuring the
transfer function. It involves the use of the reference clock as a
source of wideband excitation, in contrast to the commonly used
sinusoidal excitations at discrete frequencies. The data reported here
include the intrinsic noise of a PLL for 10 Gb/s links and the jitter
transfer function of a PLL for 12.8 Gb/s links. The measured transfer
function suggests that the PLL responded like a second order linear
system to a low noise reference clock.
Abstract: Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.