Abstract: Urban road network traffic has become one of the
most studied research topics in the last decades. This is mainly due to
the enlargement of the cities and the growing number of motor
vehicles traveling in this road network. One of the most sensitive
problems is to verify if the network is congestion-free. Another
related problem is the automatic reconfiguration of the network
without building new roads to alleviate congestions. These problems
require an accurate model of the traffic to determine the steady state
of the system. An alternative is to simulate the traffic to see if there
are congestions and when and where they occur. One key issue is to
find an adequate model for road intersections. Once the model
established, either a large scale model is built or the intersection is
represented by its performance measures and simulation for analysis.
In both cases, it is important to seek the queueing model to represent
the road intersection. In this paper, we propose to model the road
intersection as a BCMP queueing network and we compare this
analytical model against a simulation model for validation.
Abstract: A high-frequency low-power sinusoidal quadrature
oscillator is presented through the use of two 2nd-order low-pass
current-mirror (CM)-based filters, a 1st-order CM low-pass filter and
a CM bilinear transfer function. The technique is relatively simple
based on (i) inherent time constants of current mirrors, i.e. the
internal capacitances and the transconductance of a diode-connected
NMOS, (ii) a simple negative resistance RN formed by a resistor load
RL of a current mirror. Neither external capacitances nor inductances
are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V
CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature
oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz
and is current-tunable over a range of 370 MHz or 21.6 %. The
power consumption is at approximately 0.45 mW. The amplitude
matching and the quadrature phase matching are better than 0.05 dB
and 0.15°, respectively. Total harmonic distortions (THD) are less
than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise
ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a
normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The
ratio of the oscillation frequency (f0) to the unity-gain frequency (fT)
of a transistor is 0.25. Comparisons to other approaches are also
included.
Abstract: We propose a fast and robust hierarchical face detection system which finds and localizes face images with a cascade of classifiers. Three modules contribute to the efficiency of our detector. First, heterogeneous feature descriptors are exploited to enrich feature types and feature numbers for face representation. Second, a PSO-Adaboost algorithm is proposed to efficiently select discriminative features from a large pool of available features and reinforce them into the final ensemble classifier. Compared with the standard exhaustive Adaboost for feature selection, the new PSOAdaboost algorithm reduces the training time up to 20 times. Finally, a three-stage hierarchical classifier framework is developed for rapid background removal. In particular, candidate face regions are detected more quickly by using a large size window in the first stage. Nonlinear SVM classifiers are used instead of decision stump functions in the last stage to remove those remaining complex nonface patterns that can not be rejected in the previous two stages. Experimental results show our detector achieves superior performance on the CMU+MIT frontal face dataset.
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].