Abstract: Power Factor (PF) is one of the most important parameters in the electrical systems, especially in the water pumping station. The low power factor value of the water pumping stations causes penalty for the electrical bill. There are many methods use for power factor improvement. Each one of them uses a capacitor on the electrical power network. The position of the capacitors is varied depends on many factors such as; voltage level and capacitors rating. Adding capacitors on the motor terminals increase the supply power factor from 0.8 to more than 0.9 but these capacitors cause some problems for the electrical grid network, such as increasing the harmonic contents of the grid line voltage. In this paper the effects of using capacitors in the water pumping stations to improve the power factor value on the harmonic contents of the electrical grid network are studied. One of large water pumping stations in Kafr El-Shikh Governorate in Egypt was used, as a case study. The effect of capacitors on the line voltage harmonic contents is measured. The station uses capacitors to improve the PF values at the 1 lkv grid network. The power supply harmonics values are measured by a power quality analyzer at different loading conditions. The results showed that; the capacitors improved the power factor value of the feeder and its value increased than 0.9. But the THD values are increased by adding these capacitors. The harmonic analysis showed that; the 13th, 17th, and 19th harmonics orders are increased also by adding the capacitors.
Abstract: This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power
applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The proposed modulator features low power consumption (
Abstract: A modified Saleh-Valenzuela channel model has been
adapted for Ultra Wideband (UWB) system. The suggested realistic
channel is assessed by its distribution of fading amplitude and time of
arrivals. Furthermore, the propagation characteristic has been distinct
into four channel models, namely CM 1 to 4. Each are differentiate in
terms of cluster arrival rates, rays arrival rate within each cluster and
its respective constant decay rates. This paper described the
multiband OFDM system performance simulates under these
multipath conditions. Simulation work described in this paper is
based on WiMedia ECMA-368 standard, which has been deployed
for practical implementation of low cost and low power UWB
devices.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: Multicarrier transmission system such as Orthogonal
Frequency Division Multiplexing (OFDM) is a promising technique
for high bit rate transmission in wireless communication system.
OFDM is a spectrally efficient modulation technique that can achieve
high speed data transmission over multipath fading channels without
the need for powerful equalization techniques. However the price
paid for this high spectral efficiency and less intensive equalization
is low power efficiency. OFDM signals are very sensitive to nonlinear
effects due to the high Peak-to-Average Power Ratio (PAPR),
which leads to the power inefficiency in the RF section of the
transmitter. This paper investigates the effect of PAPR reduction on
the performance parameter of multicarrier communication system.
Performance parameters considered are power consumption of Power
Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier
efficiency, SNR of DAC and BER performance of the system.
From our analysis it is found that irrespective of PAPR reduction
technique being employed, the power consumption of PA and DAC
reduces and power amplifier efficiency increases due to reduction in
PAPR. Moreover, it has been shown that for a given BER performance
the requirement of Input-Backoff (IBO) reduces with reduction in
PAPR.
Abstract: In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: This paper propose a new circuit design which
monitor total leakage current during standby mode and generates the
optimal reverse body bias voltage, by using the adaptive body bias
(ABB) technique to compensate die-to-die parameter variations.
Design details of power monitor are examined using simulation
framework in 65nm and 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 10 μW for 32nm technology and
about 12 μW for 65nm technology at the same power supply voltage
as the core power supply. Moreover the results show that our
proposed circuit design is not far sensitive to the temperature
variations and also process variations. Besides, uses the simple
blocks which offer good sensitivity, high speed, the continuously
feedback loop.
Abstract: This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.
Abstract: In this paper we present a novel design of a wearable
electronic textile. After defining a special application, we used the
specifications of some low power, tiny elements including sensors,
microcontrollers, transceivers, and a fault tolerant special topology to
have the most reliability as well as low power consumption and
longer lifetime. We have considered two different conditions as
normal and bodily critical conditions and set priorities for using
different sensors in various conditions to have a longer effective
lifetime.
Abstract: In this present work, the development of an avionics
system for flight data collection of a Raptor 30 V2 is carried out. For the data acquisition both onground and onboard avionics systems are developed for testing of a small-scale Unmanned Aerial Vehicle
(UAV) helicopter. The onboard avionics record the helicopter state
outputs namely accelerations, angular rates and Euler angles, in real time, and the on ground avionics system record the inputs given to
the radio controlled helicopter through a transmitter, in real time. The avionic systems are designed and developed taking into consideration
low weight, small size, anti-vibration, low power consumption, and easy interfacing. To mitigate the medium frequency vibrations
embedded on the UAV helicopter during flight, a damper is designed
and its performance is evaluated. A number of flight tests are carried
out and the data obtained is then analyzed for accuracy and repeatability and conclusions are inferred.
Abstract: Factoring Boolean functions is one of the basic operations in algorithmic logic synthesis. A novel algebraic factorization heuristic for single-output combinatorial logic functions is presented in this paper and is developed based on the set theory paradigm. The impact of factoring is analyzed mainly from a low power design perspective for standard cell based digital designs in this paper. The physical implementation of a number of MCNC/IWLS combinational benchmark functions and sub-functions are compared before and after factoring, based on a simple technology mapping procedure utilizing only standard gate primitives (readily available as standard cells in a technology library) and not cells corresponding to optimized complex logic. The power results were obtained at the gate-level by means of an industry-standard power analysis tool from Synopsys, targeting a 130nm (0.13μm) UMC CMOS library, for the typical case. The wire-loads were inserted automatically and the simulations were performed with maximum input activity. The gate-level simulations demonstrate the advantage of the proposed factoring technique in comparison with other existing methods from a low power perspective, for arbitrary examples. Though the benchmarks experimentation reports mixed results, the mean savings in total power and dynamic power for the factored solution over a non-factored solution were 6.11% and 5.85% respectively. In terms of leakage power, the average savings for the factored forms was significant to the tune of 23.48%. The factored solution is expected to better its non-factored counterpart in terms of the power-delay product as it is well-known that factoring, in general, yields a delay-efficient multi-level solution.
Abstract: In this paper, we address the problem of reducing the
switching activity (SA) in on-chip buses through the use of a bus
binding technique in high-level synthesis. While many binding
techniques to reduce the SA exist, we present yet another technique for
further reducing the switching activity. Our proposed method
combines bus binding and data sequence reordering to explore a wider
solution space. The problem is formulated as a multiple traveling
salesman problem and solved using simulated annealing technique.
The experimental results revealed that a binding solution obtained
with the proposed method reduces 5.6-27.2% (18.0% on average) and
2.6-12.7% (6.8% on average) of the switching activity when compared
with conventional binding-only and hybrid binding-encoding
methods, respectively.
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: In this paper, a new approach for design of a fully
differential second order current mode continuous-time sigma-delta
modulator is presented. For circuit implementation, square root
domain (SRD) translinear loop based on floating-gate MOS
transistors that operate in saturation region is employed. The
modulator features, low supply voltage, low power consumption
(8mW) and high dynamic range (55dB). Simulation results confirm
that this design is suitable for data converters.
Abstract: IEEE 802.15.4a impulse radio-time hopping ultra wide
band (IR-TH UWB) physical layer, due to small duty cycle and very
short pulse widths is robust against multipath propagation. However,
scattering and reflections with the large number of obstacles in indoor
channel environments, give rise to dense multipath fading. It imposes
serious problem to optimum Rake receiver architectures, for which
very large number of fingers are needed. Presence of strong noise
also affects the reception of fine pulses having extremely low power
spectral density. A robust SRake receiver for IEEE 802.15.4a IRTH
UWB in dense multipath and additive white Gaussian noise
(AWGN) is proposed to efficiently recover the weak signals with
much reduced complexity. It adaptively increases the signal to noise
(SNR) by decreasing noise through a recursive least square (RLS)
algorithm. For simulation, dense multipath environment of IEEE
802.15.4a industrial non line of sight (NLOS) is employed. The power
delay profile (PDF) and the cumulative distribution function (CDF)
for the respective channel environment are found. Moreover, the error
performance of the proposed architecture is evaluated in comparison
with conventional SRake and AWGN correlation receivers. The
simulation results indicate a substantial performance improvement
with very less number of Rake fingers.
Abstract: Microwave energy can be used for drying purpose. It is unique process. It is distinctly different from conventional drying process. It is advantageous over conventional drying / heating processes. When microwave energy is used for drying purpose, the process can be accelerated with a better control to achieve uniform heating, more conversion efficiency, selective drying and ultimately improved product quality of the output. Also, less floor space and compact system are the added advantages. Existing low power microwave drying system is to be modified with suitable applicator. Appropriate sensors are to be used to measure parameters like moisture, temperature, weight of sample. Suitable high tech controller is to be used to control microwave power continuously from minimum to maximum. Phase - controller, cycle - controller and PWM - controller are some of the advanced power control techniques. It has been proposed to work on turmeric using high-tech phase controller to control the microwave power conveniently. The drying of turmeric with microwave energy employing phase controller gives better results as formulated in this paper and hence new approach of processing turmeric will open future doors of profit making to allied industries and the farmers.
Abstract: Wireless sensor networks (WSNs) consist of number
of tiny, low cost and low power sensor nodes to monitor some physical phenomenon. The major limitation in these networks is the use of non-rechargeable battery having limited power supply. The
main cause of energy consumption in such networks is
communication subsystem. This paper presents an energy efficient
Cluster Cooperative Caching at Sensor (C3S) based upon grid type clustering. Sensor nodes belonging to the same cluster/grid form a
cooperative cache system for the node since the cost for
communication with them is low both in terms of energy
consumption and message exchanges. The proposed scheme uses
cache admission control and utility based data replacement policy to
ensure that more useful data is retained in the local cache of a node.
Simulation results demonstrate that C3S scheme performs better in
various performance metrics than NICoCa which is existing
cooperative caching protocol for WSNs.
Abstract: This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.