Off-State Leakage Power Reduction by Automatic Monitoring and Control System
This paper propose a new circuit design which
monitor total leakage current during standby mode and generates the
optimal reverse body bias voltage, by using the adaptive body bias
(ABB) technique to compensate die-to-die parameter variations.
Design details of power monitor are examined using simulation
framework in 65nm and 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 10 μW for 32nm technology and
about 12 μW for 65nm technology at the same power supply voltage
as the core power supply. Moreover the results show that our
proposed circuit design is not far sensitive to the temperature
variations and also process variations. Besides, uses the simple
blocks which offer good sensitivity, high speed, the continuously
feedback loop.
[1] N. Mehta, B. Amrutur, and P. M. Grant, "Dynamic supply and threshold
voltage scaling for CMOS digital circuits using in-situ power monitor
(Periodical styleÔÇöAccepted for publication)," IEEE Transactions on
very large scale integration (VLSI) systems, to be published.
[2] H. Xu, W. Jone, and R. Vemuri "Aggressive runtime leakage control
through adaptive light-weight vth hopping with temperature and process
variation," IEEE transactions on very large scale integration (VLSI)
systems, VOL. 19, NO. 7, pp. 1319-1323, July 2011.
[3] H. Jeon, Y.-Bin Kim and M. Choi "Standby leakage power reduction
technique for nanoscale CMOS VLSI systems," IEEE Transactons
instrumentation and measurment, Vol. 59, No. 5, May 2010.
[4] N. Mehta, G. Naik, and B.Amrutur, "In-situ power monitoring scheme
and its application in dynamic voltage and threshold scaling for digital
cmos integrated circuits," ISLPED-10, pp. 259-264, August 2010.
[5] A. Sanyal, A. Rastogi, W. Chen, and S. Kundu, "An efficient technique
for leakage current estimation in nanoscaled cmos circuits incorporating
self-loading effects," IEEE Transactions on computers, VOL. 59, NO. 7,
pp. 922-932, July 2010
[6] M. Raymond, M. Ghoneima and Y. Ismail, "A dynamic power-aware
process variation calibration scheme," supported by the middle east
energy efficiency center - Intel, IEEE, 2010.
[7] H. Jeon, Y.-B. Kim, and M. Choi, "A novel technique to minimize
standby leakage power in nanoscale CMOS VLSI," In Proc. I2MTC,
Singapore, May 5-7, 2009, pp. 1372-1375.
[8] K. K. Kim and Y.-B. Kim, "A novel adaptive design methodology for
minimum leakage power considering pvt variations on nanoscale VLSI
systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 17,
No. 4, pp. 517-528, Apr. 2009.
[9] H. Mostafa, M. Anis, and M. Elmasry, "Comparative analysis of timing
yield improvement under process variations of flip-flops circuits," IEEE
Computer society annual symposium on VLSI, pp. 133- 138, 2009.
[10] M. Fujii, H. Suzuki, H. Notani, H. Makino and H. Shinohara, "On-chip
leakage monitor circuit to scan optimal reverse bias voltage for adaptive
body-bias circuit under gate induced drain leakage effect," IEEE, pp.
258-261, 2008.
[11] J. Hong Yang, G. Fang Li, and H. Lan Liu, "Off state leakage current in
nanoscale mosfet with HF-based gate dielectrics," IEEE International
nanoelectronics conference. 2008.
[12] K. K. Kim and Y.-B. Kim, "Optimal body biasing for minimum leakage
power in standby mode," IEEE, pp. 1161-1164, 2007.
[13] K. Ki Kim, Y.Bin Kim, N. Park, and M. Choi, "Leakage minimization
technique for nanoscale CMOS VLSI," IEEE Computer-Aided Design
for Emerging Technologies. pp. 322- 330, 2007.
[14] G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, "P3 (powerperformance-
process) optimization of nano-CMOS SRAM using
statistical DOE-ILP," supported in part by NSF awards CCF-0702361
and CNS-0854182, IEEE, 2010.
[15] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage
current mechanisms and leakage reduction techniques in deep submicrometer
CMOS circuits," Proc. IEEE, Vol. 91, No. 2, pp. 305-327,
Feb. 2003.
[16] C. Neau and K. Roy, "Optimal body bias selection for leakage
improvement and process compensation over different technology
generations," in Proc. ISLEP, Aug. 2003, pp. 116-121.
[17] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A.
Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of
die-to-die and within-die parameter variations on microprocessor
frequency and leakage," in Proc. ISSCC, 2002, pp. 786-789.
[1] N. Mehta, B. Amrutur, and P. M. Grant, "Dynamic supply and threshold
voltage scaling for CMOS digital circuits using in-situ power monitor
(Periodical styleÔÇöAccepted for publication)," IEEE Transactions on
very large scale integration (VLSI) systems, to be published.
[2] H. Xu, W. Jone, and R. Vemuri "Aggressive runtime leakage control
through adaptive light-weight vth hopping with temperature and process
variation," IEEE transactions on very large scale integration (VLSI)
systems, VOL. 19, NO. 7, pp. 1319-1323, July 2011.
[3] H. Jeon, Y.-Bin Kim and M. Choi "Standby leakage power reduction
technique for nanoscale CMOS VLSI systems," IEEE Transactons
instrumentation and measurment, Vol. 59, No. 5, May 2010.
[4] N. Mehta, G. Naik, and B.Amrutur, "In-situ power monitoring scheme
and its application in dynamic voltage and threshold scaling for digital
cmos integrated circuits," ISLPED-10, pp. 259-264, August 2010.
[5] A. Sanyal, A. Rastogi, W. Chen, and S. Kundu, "An efficient technique
for leakage current estimation in nanoscaled cmos circuits incorporating
self-loading effects," IEEE Transactions on computers, VOL. 59, NO. 7,
pp. 922-932, July 2010
[6] M. Raymond, M. Ghoneima and Y. Ismail, "A dynamic power-aware
process variation calibration scheme," supported by the middle east
energy efficiency center - Intel, IEEE, 2010.
[7] H. Jeon, Y.-B. Kim, and M. Choi, "A novel technique to minimize
standby leakage power in nanoscale CMOS VLSI," In Proc. I2MTC,
Singapore, May 5-7, 2009, pp. 1372-1375.
[8] K. K. Kim and Y.-B. Kim, "A novel adaptive design methodology for
minimum leakage power considering pvt variations on nanoscale VLSI
systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 17,
No. 4, pp. 517-528, Apr. 2009.
[9] H. Mostafa, M. Anis, and M. Elmasry, "Comparative analysis of timing
yield improvement under process variations of flip-flops circuits," IEEE
Computer society annual symposium on VLSI, pp. 133- 138, 2009.
[10] M. Fujii, H. Suzuki, H. Notani, H. Makino and H. Shinohara, "On-chip
leakage monitor circuit to scan optimal reverse bias voltage for adaptive
body-bias circuit under gate induced drain leakage effect," IEEE, pp.
258-261, 2008.
[11] J. Hong Yang, G. Fang Li, and H. Lan Liu, "Off state leakage current in
nanoscale mosfet with HF-based gate dielectrics," IEEE International
nanoelectronics conference. 2008.
[12] K. K. Kim and Y.-B. Kim, "Optimal body biasing for minimum leakage
power in standby mode," IEEE, pp. 1161-1164, 2007.
[13] K. Ki Kim, Y.Bin Kim, N. Park, and M. Choi, "Leakage minimization
technique for nanoscale CMOS VLSI," IEEE Computer-Aided Design
for Emerging Technologies. pp. 322- 330, 2007.
[14] G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, "P3 (powerperformance-
process) optimization of nano-CMOS SRAM using
statistical DOE-ILP," supported in part by NSF awards CCF-0702361
and CNS-0854182, IEEE, 2010.
[15] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage
current mechanisms and leakage reduction techniques in deep submicrometer
CMOS circuits," Proc. IEEE, Vol. 91, No. 2, pp. 305-327,
Feb. 2003.
[16] C. Neau and K. Roy, "Optimal body bias selection for leakage
improvement and process compensation over different technology
generations," in Proc. ISLEP, Aug. 2003, pp. 116-121.
[17] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A.
Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of
die-to-die and within-die parameter variations on microprocessor
frequency and leakage," in Proc. ISSCC, 2002, pp. 786-789.
@article{"International Journal of Information, Control and Computer Sciences:58710", author = "S. Abdollahi Pour and M. Saneei", title = "Off-State Leakage Power Reduction by Automatic Monitoring and Control System", abstract = "This paper propose a new circuit design which
monitor total leakage current during standby mode and generates the
optimal reverse body bias voltage, by using the adaptive body bias
(ABB) technique to compensate die-to-die parameter variations.
Design details of power monitor are examined using simulation
framework in 65nm and 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 10 μW for 32nm technology and
about 12 μW for 65nm technology at the same power supply voltage
as the core power supply. Moreover the results show that our
proposed circuit design is not far sensitive to the temperature
variations and also process variations. Besides, uses the simple
blocks which offer good sensitivity, high speed, the continuously
feedback loop.", keywords = "leakage current, leakage power monitor, body
biasing, low power", volume = "6", number = "1", pages = "79-7", }
