Abstract: An approach and its implementation in 0.18 m CMOS process of the multichannel ASIC for capacitive (up to 30 pF) sensors are described in the paper. The main design aim was to study an analog data-driven architecture. The design was done for an analog derandomizing function of the 128 to 16 structure. That means that the ASIC structure should provide a parallel front-end readout of 128 input analog sensor signals and after the corresponding fast commutation with appropriate arbitration logic their processing by means of 16 output chains, including analog-to-digital conversion. The principal feature of the ASIC is a low power consumption within 2 mW/channel (including a 9-bit 20Ms/s ADC) at a maximum average channel hit rate not less than 150 kHz.
Abstract: Sensor relocation is to repair coverage holes caused by node failures. One way to repair coverage holes is to find redundant nodes to replace faulty nodes. Most researches took a long time to find redundant nodes since they randomly scattered redundant nodes around the sensing field. To record the precise position of sensor nodes, most researches assumed that GPS was installed in sensor nodes. However, high costs and power-consumptions of GPS are heavy burdens for sensor nodes. Thus, we propose a fast sensor relocation algorithm to arrange redundant nodes to form redundant walls without GPS. Redundant walls are constructed in the position where the average distance to each sensor node is the shortest. Redundant walls can guide sensor nodes to find redundant nodes in the minimum time. Simulation results show that our algorithm can find the proper redundant node in the minimum time and reduce the relocation time with low message complexity.
Abstract: Logistics is part of the supply chain processes that
plans, implements, and controls the efficient and effective forward
and reverse flow and storage of goods, services, and related
information between the point of origin and the point of consumption
in order to meet customer requirements. This research aims to
investigate the current status and future direction of the use of
Information Technology (IT) for logistics, focusing on Supply Chain
Management (SCM) and E-Commerce adoption in Malaysia.
Therefore, this research stresses on the type of technology being
adopted, factors, benefits and barriers affecting the innovation in
SCM and E-Commerce technology adoption among Logistics
Service Providers (LSP). A mailed questionnaire survey was
conducted to collect data from 265 logistics companies in Johor. The
research revealed a high level of SCM technology adoption among
LSP as they had adopted SCM technology in various business
processes while they perceived a high level of benefits from SCM
adoption.
Abstract: The wireless sensor networks have been extensively
deployed and researched. One of the major issues in wireless sensor
networks is a developing energy-efficient clustering protocol.
Clustering algorithm provides an effective way to prolong the lifetime
of a wireless sensor networks. In the paper, we compare several
clustering protocols which significantly affect a balancing of energy
consumption. And we propose an Energy-Efficient Distributed
Unequal Clustering (EEDUC) algorithm which provides a new way of
creating distributed clusters. In EEDUC, each sensor node sets the
waiting time. This waiting time is considered as a function of residual
energy, number of neighborhood nodes. EEDUC uses waiting time to
distribute cluster heads. We also propose an unequal clustering
mechanism to solve the hot-spot problem. Simulation results show that
EEDUC distributes the cluster heads, balances the energy
consumption well among the cluster heads and increases the network
lifetime.
Abstract: In this paper, a alternative structure method for
continuous time sigma delta modulator is presented. In this
modulator for implementation of integrators in loop filter second
generation current conveyors are employed. The modulator is
designed in CMOS technology and features low power consumption
(65db),
and with 180khZ bandwidth. Simulation results confirm that this
design is suitable for data converters.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: Wireless Sensor networks have a wide spectrum of civil and military applications that call for secure communication such as the terrorist tracking, target surveillance in hostile environments. For the secure communication in these application areas, we propose a method for generating a hierarchical key structure for the efficient group key management. In this paper, we apply A* algorithm in generating a hierarchical key structure by considering the history data of the ratio of addition and eviction of sensor nodes in a location where sensor nodes are deployed. Thus generated key tree structure provides an efficient way of managing the group key in terms of energy consumption when addition and eviction event occurs. A* algorithm tries to minimize the number of messages needed for group key management by the history data. The experimentation with the tree shows efficiency of the proposed method.
Abstract: Natural ventilation is an important means to improve indoor thermal comfort and reduce the energy consumption. A solar chimney system is an enhancing natural draft device, which uses solar radiation to heat the air inside the chimney, thereby converting the thermal energy into kinetic energy. The present study considered some parameters such as chimney width and solar intensity, which were believed to have a significant effect on space ventilation. Fluent CFD software was used to predict buoyant air flow and flow rates in the cavities. The results were compared with available published experimental and theoretical data from the literature. There was an acceptable trend match between the present results and the published data for the room air change per hour, ACH. Further, it was noticed that the solar intensity has a more significant effect on ACH.
Abstract: During recent years, attention in 'Green Computing'
has moved research into energy-saving techniques for home
computers to enterprise systems' Client and Server machines. Saving
energy or reduction of carbon footprints is one of the aspects of
Green Computing. The research in the direction of Green Computing
is more than just saving energy and reducing carbon foot prints. This
study provides a brief account of Green Computing. The emphasis of
this study is on current trends in Green Computing; challenges in the
field of Green Computing and the future trends of Green Computing.
Abstract: Passive systems were born with the purpose of the
greatest exploitation of solar energy in cold climates and high
altitudes. They spread themselves until the 80-s all over the world
without any attention to the specific climate and the summer
behavior; this caused the deactivation of the systems due to a series
of problems connected to the summer overheating, the complex
management and the rising of the dust.
Until today the European regulation limits only the winter
consumptions without any attention to the summer behavior but, the
recent European EN 15251 underlines the relevance of the indoor
comfort, and the necessity of the analytic studies validation by
monitoring case studies.
In the porpose paper we demonstrate that the solar wall is an
efficient system both from thermal comfort and energy saving point
of view and it is the most suitable for our temperate climates because
it can be used as a passive cooling sistem too. In particular the paper
present an experimental and numerical analisys carried out on a case
study with nine different solar passive systems in Ancona, Italy.
We carried out a detailed study of the lodging provided by the
solar wall by the monitoring and the evaluation of the indoor
conditions.
Analyzing the monitored data, on the base of recognized models
of comfort (ISO, ASHRAE, Givoni-s BBCC), is emerged that the
solar wall has an optimal behavior in the middle seasons. In winter
phase this passive system gives more advantages in terms of energy
consumptions than the other systems, because it gives greater heat
gain and therefore smaller consumptions. In summer, when outside
air temperature return in the mean seasonal value, the indoor comfort
is optimal thanks to an efficient transversal ventilation activated from
the same wall.
Abstract: As the data-driven economy is growing faster than
ever and the demand for energy is being spurred, we are facing
unprecedented challenges of improving energy efficiency in data
centers. Effectively maximizing energy efficiency or minimising the
cooling energy demand is becoming pervasive for data centers. This
paper investigates overall energy consumption and the energy
efficiency of cooling system for a data center in Finland as a case
study. The power, cooling and energy consumption characteristics
and operation condition of facilities are examined and analysed.
Potential energy and cooling saving opportunities are identified and
further suggestions for improving the performance of cooling system
are put forward. Results are presented as a comprehensive evaluation
of both the energy performance and good practices of energy
efficient cooling operations for the data center. Utilization of an
energy recovery concept for cooling system is proposed. The
conclusion we can draw is that even though the analysed data center
demonstrated relatively high energy efficiency, based on its power
usage effectiveness value, there is still a significant potential for
energy saving from its cooling systems.
Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.
Abstract: A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage,
Control Logic (CL) makes the clocks of the switching units
of the register inactive for a time period when output from
them is going to be same as previous one and thus reducing
unnecessary switching of the flip-flops. And at second stage,
the LFSR reorders the test vectors by interchanging the bit
with its next and closest neighbor bit. It keeps fault coverage
capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power
while shifting operation.
Abstract: In recent years, there has been an increasing interest in using daylight to save energy in buildings. In tropical regions, daylighting is always an energy saver. On the other hand, daylight provides visual comfort. According to standards, it shows that many criteria should be taken into consideration in order to have daylight utilization and visual comfort. The current standard in Malaysia, MS 1525 does not provide sufficient guideline. Hence, more research is needed on daylight performance. If architects do not consider daylight design, it not only causes inconvenience in working spaces but also causes more energy consumption as well as environmental pollution. This research had surveyed daylight performance in 5 selected office buildings from different area of Malaysian through experimental method. Several parameters of daylight quality such as daylight factor, surface luminance and surface luminance ratio were measured in different rooms in each building. The result of this research demonstrated that most of the buildings were not designed for daylight utilization. Therefore, it is very important that architects follow the daylight design recommendation to reduce consumption of electric power for artificial lighting while the sufficient quality of daylight is available.
Abstract: In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.
Abstract: In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.
Abstract: This paper describes a platform that faces the main
research areas for e-learning educational contents. Reusability tackles
the possibility to use contents in different courses reducing costs and
exploiting available data from repositories. In our approach the
production of educational material is based on templates to reuse
learning objects. In terms of interoperability the main challenge lays
on reaching the audience through different platforms. E-learning
solution must track social consumption evolution where nowadays
lots of multimedia contents are accessed through the social networks.
Our work faces it by implementing a platform for generation of
multimedia presentations focused on the new paradigm related to
social media. The system produces videos-courses on top of web
standard SMIL (Synchronized Multimedia Integration Language)
ready to be published and shared. Regarding interfaces it is
mandatory to satisfy user needs and ease communication. To
overcome it the platform deploys virtual teachers that provide natural
interfaces while multimodal features remove barriers to pupils with
disabilities.
Abstract: Subdivision surfaces were applied to the entire
meshes in order to produce smooth surfaces refinement from coarse
mesh. Several schemes had been introduced in this area to provide a
set of rules to converge smooth surfaces. However, to compute and
render all the vertices are really inconvenient in terms of memory
consumption and runtime during the subdivision process. It will lead
to a heavy computational load especially at a higher level of
subdivision. Adaptive subdivision is a method that subdivides only at
certain areas of the meshes while the rest were maintained less
polygons. Although adaptive subdivision occurs at the selected areas,
the quality of produced surfaces which is their smoothness can be
preserved similar as well as regular subdivision. Nevertheless,
adaptive subdivision process burdened from two causes; calculations
need to be done to define areas that are required to be subdivided and
to remove cracks created from the subdivision depth difference
between the selected and unselected areas. Unfortunately, the result
of adaptive subdivision when it reaches to the higher level of
subdivision, it still brings the problem with memory consumption.
This research brings to iterative process of adaptive subdivision to
improve the previous adaptive method that will reduce memory
consumption applied on triangular mesh. The result of this iterative
process was acceptable better in memory and appearance in order to
produce fewer polygons while it preserves smooth surfaces.
Abstract: This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).
Abstract: Wireless sensor networks include small nodes which
have sensing ability; calculation and connection extend themselves
everywhere soon. Such networks have source limitation on
connection, calculation and energy consumption. So, since the nodes
have limited energy in sensor networks, the optimized energy
consumption in these networks is of more importance and has created
many challenges. The previous works have shown that by organizing
the network nodes in a number of clusters, the energy consumption
could be reduced considerably. So the lifetime of the network would
be increased. In this paper, we used the Queen-bee algorithm to
create energy efficient clusters in wireless sensor networks. The
Queen-bee (QB) is similar to nature in that the queen-bee plays a
major role in reproduction process. The QB is simulated with J-sim
simulator. The results of the simulation showed that the clustering by
the QB algorithm decreases the energy consumption with regard to
the other existing algorithms and increases the lifetime of the
network.