Abstract: This paper presents a fault-tolerant implementation for
adder schemes using the dual duplication code. To prove the
efficiency of the proposed method, the circuit is simulated in double
pass transistor CMOS 32nm technology and some transient faults are
voluntary injected in the Layout of the circuit. This fully differential
implementation requires only 20 transistors which mean that the
proposed design involves 28.57% saving in transistor count
compared to standard CMOS technology.
Abstract: The aim of this study was to design and simulate a
particular type of Asynchronous State Machine (ASM), namely a
‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz.
The design task involved two main stages: firstly, designing a 4-bit
binary counter using J-K flip flops as the timing signal and,
subsequently, attaining the digital logic by deploying ASM design
process. The TLC was designed such that it showed a sequence of
three different colours, i.e. red, yellow and green, corresponding to
set thresholds by deploying the least number of AND, OR and NOT
gates possible. The software Multisim was deployed to design such
circuit and simulate it for circuit troubleshooting in order for it to
display the output sequence of the three different colours on the
traffic light in the correct order. A clock signal, an asynchronous 4-
bit binary counter that was designed through the use of J-K flip flops
along with an ASM were used to complete this sequence, which was
programmed to be repeated indefinitely. Eventually, the circuit was
debugged and optimized, thus displaying the correct waveforms of
the three outputs through the logic analyser. However, hazards
occurred when the frequency was increased to 10 MHz. This was
attributed to delays in the feedback being too high.