A Fault-Tolerant Full Adder in Double Pass CMOS Transistor

This paper presents a fault-tolerant implementation for
adder schemes using the dual duplication code. To prove the
efficiency of the proposed method, the circuit is simulated in double
pass transistor CMOS 32nm technology and some transient faults are
voluntary injected in the Layout of the circuit. This fully differential
implementation requires only 20 transistors which mean that the
proposed design involves 28.57% saving in transistor count
compared to standard CMOS technology.

• Abdelmonaem Ayachi
• Belgacem Hamdi

• Semiconductors
• digital electronics
• double pass transistor technology
• Full adder
• fault tolerance.

[1] Ko, U., P. Balsara and W. Lee, 1995. “Low-power design techniques for
high performance CMOS adders,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., (2):327-333.
[2] Song, P.J. and G. De Micheli, “Circuit and architecture trade-offs for
high speed multiplication,” IEEE J. Solid-Sate Circuit, 26(9): 1184-1198,
1991.
[3] Junming, L., S. Yan, L. Zhenghui and W. Ling, 2001. “A Novel 10-
Transistor Low-Power High- Speed Full Adder Cell, In: Proceedings of
IEEE 6th International Conf. Solid-State & Integrated-Circuit
Technology, Shanghai Jiao Tong Univ., China, pp. 1155-1158.
[4] Shalem, R., E. John and L. K. John, “A novel low power energy
recovery full adder cell,” In: Proceedings of The Ninth Great Lakes
Symposium on VLSI, Ann Arbor, MI, USA, pp. 380–383, 1999.
[5] Khatibzadeh, A. and K. Raahemifar, “Study and comparison of full
adder cells based on the standard static cmos logic,” In: IEEE Electrical
and Computer Eng. Canadian Conference, pp. 2139-2142, 2004. [6] Tzartzanis, G. L. S. o. V. N. and W. C. Athas, “Design and analysis of a
low-power energy-recovery adder,” In: Proceedings of The Fifth Great
Lakes Symposium on VLSI pp. 66- 69, 1995.
[7] H. T. Bui, Y. Wang, Y. Jiang, 2002. “ Design and analysis of low power
10 -transistor Full Adders using nowel XOR-XNOR gates,” IEEE
Transactions on Circuits & Systems II 49, pp. 25-30.
[8] V. Foroutan, K. Navi.M. Haghparast, 2008. “A New Low Power
Dynamic Full Adder Cell Based on Majority Function,” World Applied
Sciences Journal 4, pp. 133-141.
[9] Y. Jiang, A. Al-Sheraidah, Y. Yang, E. Sha and J. G. Chung, “A novel
multiplexer-Based Low-Power Full Adder,” in IEEE Trans. on circuits
and system II, Vol. 51, No. 7, July 2004, pp. 345-348.
[10] A. Shams, T. Darwish, M. Bayoumi, “Performance Analysis of Low
Power 1-bit CMOS Full-adder Cells,” IEEE Transactions on Very Large
Scale Integration (VLSI)Systems, 10(1), 2002 February, 20–29.
[11] C. H. Chang, J. Gu, M. Zhang, “A Review of 0.18 mm Full adder
Performances for Tree Structure Arithmetic Circuits,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, 13 (6),
2005 June.
[12] S. Issam, A. Khater, A. Bellaouar, M. I. Elmasry, “Circuit Techniques
for CMOS Low-power High-performance Multipliers,” IEEE Journal of
Solid-State Circuits, 31, 1996 October, 1535–1544.
[13] R. Zimmermann, W. Fichtner, “Low-power Logic Styles: CMOS Versus
Pass-transistor Logic,” IEEE Journal of Solid-State Circuits, 32 (7),
1997, 1079–1089.
[14] M. M. Vai, “VLSI Design,” CRC, Boca Raton, FL, 2001.
[15] N. Weste, K. Eshraghian, “Principles of CMOS VLSI Design: A System
Perspective,” Addison Wesley, Reading, MA, 1993.
[16] M. Suzuki, N. Ohkubo, T.Yamanaka, A. Shimizu, and K. Sasaki, “A
1.5ns 32b CMOS ALU in double pass-transistor logic,” in Proc. 1993
IEEE Int. Solid-State Circuits Conf., Feb. 1993, pp. 90–91.
[17] Y. Jiang, A. Al-Sheraidah, Y. Yang, E. Sha and J. G. Chung, “A novel
multiplexer-Based Low-Power Full Adder,” in IEEE Trans. on circuits
and system II, Vol. 51, No. 7, July 2004, pp. 345-348.
[18] K. Navi, M. R. Saatchi and O. Dael, „A High-Speed Hybrid Full Adder‟,
in European Journal of Scientific Research, Vol .26. No.1, 2009, pp. 29-
33.
[19] I. Koren and C. M. Krishna, “Fault-Tolerant Systems,” San Francisco,
CA, USA: Morgan-Kaufman Publishers, 2007.
[20] D. K. Pradhan, “Fault Tolerant Computer System Design,” Prentice Hall,
Upper Saddle River, NJ, USA, 1996.
[21] M. Goessel and F. Graf, “Error Detection Circuits,” McGraw-Hill,
London, 1993.
[22] M. Nicolaids and Y. Zorian, “On-Line Testing for VLSI – A
Compendium of Approaches,” JETTA, Vol. 12, No. 1-2, Feb.-Apr. 1998,
pp. 7-20.
[23] Goran Lj Djordjevic, Mile K. Stojcev, Tatjana R. Stankovic, “Approach
to partially self-checking combinational circuits design,”
Microelectronics Journal 35 (2004) pp. 945–952.
[24] W. W. Peterson, “On checking an Adder,” IBM J. Res. Develop. 2,
April 1958, pp. 166-168.
[25] Avizienis, “Arithmetic Algorithms for Error-Coded Operands,” in IEEE
Trans. on Computer, Vol. C-22, No.6, June. 1973, pp. 567-572.
[26] O. N. Garcia and T. R. Ν. Rao, “On the method of checking logical
operations,” in 2nd Annual Princeton Conf. Inform. Sci. Sys., 1968, pp.
89-95.
[27] F. F. Sellers, M. Y. Hsiao and L. W. Bearson, “Error Detecting Logic for
Digital Computers,” Mc GRAW-HILL publishers, New-York, 1968.
[28] M. Nicolaidis, „Efficient implementations of self-checking adders and
ALUs‟, in 23rd International Symposium on Fault-Tolerant Computing,
June 1993, pp. 586-595.
[29] M. Lubaszewski., S. Mir, V. Kolarik, C. Nielsen and B. Courtois,
“Design of self-checking fully differential circuits and boards,” in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, Volume
8, Issue 2, Apr 2000, pp. 113 -128.
[30] J. D. Lee, Y. J. Yoony, K. H. Leez, B. G. Park, “Application of dynamic
pass- transistor logic to an 8-bit multiplier,” Journal of the Korean
Physical Society, Vol. 38, No. 3, March 2001, pp. 220_223.
[31] M. Aliotoa, G. Di Cataldob, G. Palumbob, “Mixed Full Adder
topologies for high-performance low-power arithmetic circuits,”
Microelectronics Journal 38. pp. 130–139. 2007.
[32] Pooja Mendiratta & Garima Bakshi, “A Low-power Full-adder Cell
based on Static CMOS Inverter,” International Journal of Electronics
Engineering, 2(1), 2010, pp. 143-149.
[33] N. Ohkubo et al., “A 4.4 ns CMOS 54*54-b multiplier using pass
transistor multiplexer,” IEEE J. Solid-State Circuits, vol. 30, pp. 251–
257, Mar. 1995.
[34] M. S. Suzukiet a l . , “A 1.5-ns 32-b CMOS ALU in DoublePass-
Transistor Logic,” IEEE J. Solid-State Circuits, v o l . 28, no. 11,
pp. 1145-1151,November 1993.
[35] A. Bellaouar andM. I. Elmasry, “Low-PowerDigital VLSI Design:
Circuits and Systems”, Kluwer, Norwell, MA, 1995.
[36] M. Nicolaidis, “On-line testing for VLSI: state of the art and trends,”
Integration, the VLSI Journal, Volume 26, Issues 1-2, 1 December 1998,
pp. 197-209.
[37] Marc Hunger and Sybille Hellebrand, “Verification and Analysis of
Self-Checking Properties through ATPG,” 14th IEEE International On-
Line Testing Symposium, Rhodes, Greece, 6 - 9 July 2008.
[38] P. Oikonomakos and M. Zwolinski, “On the Design of Self-Checking
Controllers with Data path Interactions,” in IEEE Transactions on
Computers, Volume 55, No 11, Nov 2006, pp. 1423 – 1434.
[39] D. A. Anderson, “Design of self-checking digital networks using coding
techniques”, Univ. Illinois Coordinated Sci. Lab., Urbana, IL, Tech. Rep.
R-527, Sept. 1971.
[40] E. Sicard, “Microwind and Dsch version 3.1,” INSA Toulouse, ISBN 2-
87649-050-1, Dec 2006.