Abstract: This paper proposes a neural network weights and
topology optimization using genetic evolution and the
backpropagation training algorithm. The proposed crossover and
mutation operators aims to adapt the networks architectures and
weights during the evolution process. Through a specific inheritance
procedure, the weights are transmitted from the parents to their
offsprings, which allows re-exploitation of the already trained
networks and hence the acceleration of the global convergence of the
algorithm. In the preprocessing phase, a new feature extraction
method is proposed based on Legendre moments with the Maximum
entropy principle MEP as a selection criterion. This allows a global
search space reduction in the design of the networks. The proposed
method has been applied and tested on the well known MNIST
database of handwritten digits.
Abstract: IPsec protocol[1] is a set of security extensions
developed by the IETF and it provides privacy and authentication
services at the IP layer by using modern cryptography. In this paper,
we describe both of H/W and S/W architectures of our router system,
SRS-10. The system is designed to support high performance routing
and IPsec VPN. Especially, we used Cavium-s CN2560 processor to
implement IPsec processing in inline-mode.
Abstract: The main goal of this seminal paper is to introduce the
application of Wireless Sensor Networks (WSN) in long distance
infrastructure monitoring (in particular in pipeline infrastructure
monitoring) – one of the on-going research projects by the Wireless
Communication Research Group at the department of Electronic and
Computer Engineering, Nnamdi Azikiwe University, Awka. The
current sensor network architectures for monitoring long distance
pipeline infrastructures are previewed. These are wired sensor
networks, RF wireless sensor networks, integrated wired and wireless
sensor networks. The reliability of these architectures is discussed.
Three reliability factors are used to compare the architectures in
terms of network connectivity, continuity of power supply for the
network, and the maintainability of the network. The constraints and
challenges of wireless sensor networks for monitoring and protecting
long distance pipeline infrastructure are discussed.
Abstract: The performance of sensor-less controlled induction
motor drive depends on the accuracy of the estimated speed.
Conventional estimation techniques being mathematically complex
require more execution time resulting in poor dynamic response. The
nonlinear mapping capability and powerful learning algorithms of
neural network provides a promising alternative for on-line speed
estimation. The on-line speed estimator requires the NN model to be
accurate, simpler in design, structurally compact and computationally
less complex to ensure faster execution and effective control in real
time implementation. This in turn to a large extent depends on the
type of Neural Architecture. This paper investigates three types of
neural architectures for on-line speed estimation and their
performance is compared in terms of accuracy, structural
compactness, computational complexity and execution time. The
suitable neural architecture for on-line speed estimation is identified
and the promising results obtained are presented.
Abstract: This paper presents a mean for reducing the torque
variation during the revolution of a vertical-axis wind turbine
(VAWT) by increasing the blade number. For this purpose, twodimensional
CDF analysis have been performed on a straight-bladed
Darreius-type rotor. After describing the computational model, a
complete campaign of simulations based on full RANS unsteady
calculations is proposed for a three, four and five-bladed rotor
architecture characterized by a NACA 0025 airfoil. For each
proposed rotor configuration, flow field characteristics are
investigated at several values of tip speed ratio, allowing a
quantification of the influence of blade number on flow geometric
features and dynamic quantities, such as rotor torque and power.
Finally, torque and power curves are compared for the analyzed
architectures, achieving a quantification of the effect of blade number
on overall rotor performance.
Abstract: Avionics software is safe-critical embedded software
and its architecture is evolving from traditional federated architectures
to Integrated Modular Avionics (IMA) to improve resource usability.
ARINC 653 (Avionics Application Standard Software Interface) is a
software specification for space and time partitioning in Safety-critical
avionics Real-time operating systems. Arinc653 uses two-level
scheduling strategies, but current modeling tools only apply to simple
problems of Arinc653 two-level scheduling, which only contain time
property. In avionics industry, we are always manually allocating
tasks and calculating the timing table of a real-time system to ensure
it-s running as we design. In this paper we represent an automatically
generating strategy which applies to the two scheduling problems with
dependent constraints in Arinc653 partition run-time environment. It
provides the functionality of automatic generation from the task and partition models to scheduling policy through allocating the tasks to the partitions while following the constraints, and then we design a simulating mechanism to check whether our policy is schedulable or
not
Abstract: A set of Artificial Neural Network (ANN) based methods
for the design of an effective system of speech recognition of
numerals of Assamese language captured under varied recording
conditions and moods is presented here. The work is related to
the formulation of several ANN models configured to use Linear
Predictive Code (LPC), Principal Component Analysis (PCA) and
other features to tackle mood and gender variations uttering numbers
as part of an Automatic Speech Recognition (ASR) system in
Assamese. The ANN models are designed using a combination of
Self Organizing Map (SOM) and Multi Layer Perceptron (MLP)
constituting a Learning Vector Quantization (LVQ) block trained in a
cooperative environment to handle male and female speech samples
of numerals of Assamese- a language spoken by a sizable population
in the North-Eastern part of India. The work provides a comparative
evaluation of several such combinations while subjected to handle
speech samples with gender based differences captured by a microphone
in four different conditions viz. noiseless, noise mixed, stressed
and stress-free.
Abstract: The paper describes a self supervised parallel self organizing neural network (PSONN) architecture for true color image segmentation. The proposed architecture is a parallel extension of the standard single self organizing neural network architecture (SONN) and comprises an input (source) layer of image information, three single self organizing neural network architectures for segmentation of the different primary color components in a color image scene and one final output (sink) layer for fusion of the segmented color component images. Responses to the different shades of color components are induced in each of the three single network architectures (meant for component level processing) by applying a multilevel version of the characteristic activation function, which maps the input color information into different shades of color components, thereby yielding a processed component color image segmented on the basis of the different shades of component colors. The number of target classes in the segmented image corresponds to the number of levels in the multilevel activation function. Since the multilevel version of the activation function exhibits several subnormal responses to the input color image scene information, the system errors of the three component network architectures are computed from some subnormal linear index of fuzziness of the component color image scenes at the individual level. Several multilevel activation functions are employed for segmentation of the input color image scene using the proposed network architecture. Results of the application of the multilevel activation functions to the PSONN architecture are reported on three real life true color images. The results are substantiated empirically with the correlation coefficients between the segmented images and the original images.
Abstract: This work concerns the measurements of a Bulk
Acoustic Waves (BAW) emission filter S parameters and compare
with prototypes simulated types. Thanks to HP-ADS, a co-simulation
of filters- characteristics in a digital radio-communication chain is
performed. Four cases of modulation schemes are studied in order to
illustrate the impact of the spectral occupation of the modulated
signal. Results of simulations and co-simulation are given in terms of
Error Vector Measurements to be useful for a general sensibility
analysis of 4th/3rd Generation (G.) emitters (wideband QAM and
OFDM signals)
Abstract: For today-s and future wireless communications applications,
more and more data traffic has to be transmitted with
growing speed and quality demands. The analog front-end of any
mobile device has to cope with very hard specifications regardless
which transmission standard has to be supported. State-of-the-art
analog front-end implementations are reaching the limit of technical
feasibility. For that reason, alternative front-end architectures could
support a continuing development of mobile communications e.g.,
six-port-based front-ends [1], [2].
In this article we propose an analog front-end with high intermediate
frequency and which utilizes additive mixing instead
of multiplicative mixing. The system architecture is presented and
several spurious effects as well as their influence on the system
dimensioning are discussed. Furthermore, several issues concerning
the technical feasibility are provided and some simulation results
are discussed which show the principle functionality of the proposed
superposition heterodyne receiver.
Abstract: The Partitioned Global Address Space (PGAS) programming
paradigm offers ease-of-use in expressing parallelism
through a global shared address space while emphasizing performance
by providing locality awareness through the partitioning of
this address space. Therefore, the interest in PGAS programming
languages is growing and many new languages have emerged and
are becoming ubiquitously available on nearly all modern parallel
architectures. Recently, new parallel machines with multiple cores
are designed for targeting high performance applications. Most of the
efforts have gone into benchmarking but there are a few examples of
real high performance applications running on multicore machines.
In this paper, we present and evaluate a parallelization technique
for implementing a local DNA sequence alignment algorithm using
a PGAS based language, UPC (Unified Parallel C) on a chip
multithreading architecture, the UltraSPARC T1.
Abstract: This paper presents an architecture to assist in the
development of tools to perform experimental analysis. Existing
implementations of tools based on this architecture are also described
in this paper. These tools are applied to the real world problem of
fault attack emulation and detection in cryptographic algorithms.
Abstract: Service discovery is a very important component of Service Oriented Architectures (SOA). This paper presents two alternative approaches to customise the query results of private service registry such as Universal Description, Discovery and Integration (UDDI). The customisation is performed based on some pre-defined and/or real-time changing parameters. This work identifies the requirements, designs and additional mechanisms that must be applied to UDDI in order to support this customisation capability. We also detail the implements of the approaches and examine its performance and scalability. Based on our experimental results, we conclude that both approaches can be used to customise registry query results, but by storing personalization parameters in external resource will yield better performance and but less scalable when size of query results increases. We believe these approaches when combined with semantics enabled service registry will enhance the service discovery methods within a private UDDI registry environment.
Abstract: This paper compares the recent transformerless ACDC
power converter architectures and provides an assessment of
each. A prototype of one of the transformerless AC-DC converter
architecture is also presented depicting the feasibility of a small form
factor, power supply design. In this paper component selection
guidelines to achieve high efficiency AC-DC power conversion are
also discussed.
Abstract: Many artificial intelligence (AI) techniques are inspired
by problem-solving strategies found in nature. Robustness is a key
feature in many natural systems. This paper studies robustness in
artificial neural networks (ANNs) and proposes several novel, nature
inspired ANN architectures. The paper includes encouraging results
from experimental studies on these networks showing increased
robustness.
Abstract: The development of Artificial Neural Networks
(ANNs) is usually a slow process in which the human expert has to
test several architectures until he finds the one that achieves best
results to solve a certain problem. This work presents a new
technique that uses Genetic Programming (GP) for automatically
generating ANNs. To do this, the GP algorithm had to be changed in
order to work with graph structures, so ANNs can be developed. This
technique also allows the obtaining of simplified networks that solve
the problem with a small group of neurons. In order to measure the
performance of the system and to compare the results with other
ANN development methods by means of Evolutionary Computation
(EC) techniques, several tests were performed with problems based
on some of the most used test databases. The results of those
comparisons show that the system achieves good results comparable
with the already existing techniques and, in most of the cases, they
worked better than those techniques.
Abstract: A model to identify the lifetime of target tracking
wireless sensor network is proposed. The model is a static clusterbased
architecture and aims to provide two factors. First, it is to
increase the lifetime of target tracking wireless sensor network.
Secondly, it is to enable good localization result with low energy
consumption for each sensor in the network. The model consists of
heterogeneous sensors and each sensing member node in a cluster
uses two operation modes–active mode and sleep mode. The
performance results illustrate that the proposed architecture consumes
less energy and increases lifetime than centralized and dynamic
clustering architectures, for target tracking sensor network.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: Since 1992, year where Hugo de Garis has published
the first paper on Evolvable Hardware (EHW), a period of intense
creativity has followed. It has been actively researched, developed
and applied to various problems. Different approaches have been
proposed that created three main classifications: extrinsic, mixtrinsic
and intrinsic EHW. Each of these solutions has a real interest.
Nevertheless, although the extrinsic evolution generates some
excellent results, the intrinsic systems are not so advanced. This
paper suggests 3 possible solutions to implement the run-time
configuration intrinsic EHW system: FPGA-based Run-Time
Configuration system, JBits-based Run-Time Configuration system
and Multi-board functional-level Run-Time Configuration system.
The main characteristic of the proposed architectures is that they are
implemented on Field Programmable Gate Array. A comparison of
proposed solutions demonstrates that multi-board functional-level
run-time configuration is superior in terms of scalability, flexibility
and the implementation easiness.
Abstract: The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.