Abstract: Software Architecture is the basic structure of
software that states the development and advancement of a software
system. Software architecture is also considered as a significant tool
for the construction of high quality software systems. A clean design
leads to the control, value and beauty of software resulting in its
longer life while a bad design is the cause of architectural erosion
where a software evolution completely fails. This paper discusses the
occurrence of software architecture erosion and presents a set of
methods for the detection, declaration and prevention of architecture
erosion. The causes and symptoms of architecture erosion are
observed with the examples of prescriptive and descriptive
architectures and the practices used to stop this erosion are also
discussed by considering different types of software erosion and their
affects. Consequently finding and devising the most suitable
approach for fighting software architecture erosion and in some way
reducing its affect is evaluated and tested on different scenarios.
Abstract: In this paper, we propose a new packing strategy to
find a free resource for run-time mapping of application tasks to
NoC-based Heterogeneous MPSoC. The proposed strategy minimizes
the task mapping time in addition to placing the communicating tasks
close to each other. To evaluate our approach, a comparative study is
carried out for a platform containing single task supported PEs.
Experiments show that our strategy provides better results when
compared to latest dynamic mapping strategies reported in the
literature.
Abstract: Two multisensor system architectures for navigation
and guidance of small Unmanned Aircraft (UA) are presented and
compared. The main objective of our research is to design a compact,
light and relatively inexpensive system capable of providing the
required navigation performance in all phases of flight of small UA,
with a special focus on precision approach and landing, where Vision
Based Navigation (VBN) techniques can be fully exploited in a
multisensor integrated architecture. Various existing techniques for
VBN are compared and the Appearance-Based Navigation (ABN)
approach is selected for implementation. Feature extraction and
optical flow techniques are employed to estimate flight parameters
such as roll angle, pitch angle, deviation from the runway centreline
and body rates. Additionally, we address the possible synergies of
VBN, Global Navigation Satellite System (GNSS) and MEMS-IMU
(Micro-Electromechanical System Inertial Measurement Unit)
sensors, and the use of Aircraft Dynamics Model (ADM) to provide
additional information suitable to compensate for the shortcomings of
VBN and MEMS-IMU sensors in high-dynamics attitude
determination tasks. An Extended Kalman Filter (EKF) is developed
to fuse the information provided by the different sensors and to
provide estimates of position, velocity and attitude of the UA
platform in real-time. The key mathematical models describing the
two architectures i.e., VBN-IMU-GNSS (VIG) system and VIGADM
(VIGA) system are introduced. The first architecture uses VBN
and GNSS to augment the MEMS-IMU. The second mode also
includes the ADM to provide augmentation of the attitude channel.
Simulation of these two modes is carried out and the performances of
the two schemes are compared in a small UA integration scheme (i.e.,
AEROSONDE UA platform) exploring a representative cross-section
of this UA operational flight envelope, including high dynamics
manoeuvres and CAT-I to CAT-III precision approach tasks.
Simulation of the first system architecture (i.e., VIG system) shows
that the integrated system can reach position, velocity and attitude
accuracies compatible with the Required Navigation Performance
(RNP) requirements. Simulation of the VIGA system also shows
promising results since the achieved attitude accuracy is higher using
the VBN-IMU-ADM than using VBN-IMU only. A comparison of
VIG and VIGA system is also performed and it shows that the
position and attitude accuracy of the proposed VIG and VIGA
systems are both compatible with the RNP specified in the various
UA flight phases, including precision approach down to CAT-II.
Abstract: Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.
Abstract: This paper presents a novel Global Navigation Satellite System (GNSS) Avionics Based Integrity Augmentation (ABIA) system architecture suitable for civil and military air platforms, including Unmanned Aircraft Systems (UAS). Taking the move from previous research on high-accuracy Differential GNSS (DGNSS) systems design, integration and experimental flight test activities conducted at the Italian Air Force Flight Test Centre (CSV-RSV), our research focused on the development of a novel approach to the problem of GNSS ABIA for mission- and safety-critical air vehicle applications and for multi-sensor avionics architectures based on GNSS. Detailed mathematical models were developed to describe the main causes of GNSS signal outages and degradation in flight, namely: antenna obscuration, multipath, fading due to adverse geometry and Doppler shift. Adopting these models in association with suitable integrity thresholds and guidance algorithms, the ABIA system is able to generate integrity cautions (predictive flags) and warnings (reactive flags), as well as providing steering information to the pilot and electronic commands to the aircraft/UAS flight control systems. These features allow real-time avoidance of safety-critical flight conditions and fast recovery of the required navigation performance in case of GNSS data losses. In other words, this novel ABIA system addresses all three cornerstones of GNSS integrity augmentation in mission- and safety-critical applications: prediction (caution flags), reaction (warning flags) and correction (alternate flight path computation).
Abstract: Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several architectures have been proposed as bus architectures for a GALS system : shared bus, segmented bus, ring bus, and so on. In this study, we propose a ring segmented bus architecture which is a combination of segmented bus and ring bus architecture with the aim of throughput enhancement. In a segmented bus architecture, segments are connected in series. By connecting the segments at the end of the bus and constructing the ring bus, it becomes possible to allocate a channel of the bus bidirectionally. The bus channel is allocated to the shortest path between segments. We consider a metastable operation caused by asynchronous communication between segments and a burst transfer between segments. According to the result of simulation, it is shown that the GALS system designed by the proposed method has the desired operations.
Abstract: Video streaming over lossy IP networks is very
important issues, due to the heterogeneous structure of networks.
Infrastructure of the Internet exhibits variable bandwidths, delays,
congestions and time-varying packet losses. Because of variable
attributes of the Internet, video streaming applications should not
only have a good end-to-end transport performance but also have a
robust rate control, furthermore multipath rate allocation mechanism.
So for providing the video streaming service quality, some other
components such as Bandwidth Estimation and Adaptive Rate
Controller should be taken into consideration. This paper gives an
overview of video streaming concept and bandwidth estimation tools
and then introduces special architectures for bandwidth adaptive
video streaming. A bandwidth estimation algorithm – pathChirp,
Optimized Rate Controllers and Multipath Rate Allocation Algorithm
are considered as all-in-one solution for video streaming problem.
This solution is directed and optimized by a decision center which is
designed for obtaining the maximum quality at the receiving side.
Abstract: This paper considers the benefits gained by using an
efficient quality of service management such as DiffServ technique to
improve the performance of military communications. Low delay and
no blockage must be achieved especially for real time tactical data.
All traffic flows generated by different applications do not need same
bandwidth, same latency, same error ratio and this scalable technique
of packet management based on priority levels is analysed. End to
end architectures supporting various traffic flows and including lowbandwidth
and high-delay HF or SHF military links as well as
unprotected Internet sub domains are studied. A tuning of Diffserv
parameters is proposed in accordance with different loads of various
traffic and different operational situations.
Abstract: .Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented
Abstract: With the exponential rise in the number of multimedia
applications available, the best-effort service provided by the Internet
today is insufficient. Researchers have been working on new
architectures like the Next Generation Network (NGN) which, by
definition, will ensure Quality of Service (QoS) in an all-IP based
network [1]. For this approach to become a reality, reservation of
bandwidth is required per application per user. WiMAX (Worldwide
Interoperability for Microwave Access) is a wireless communication
technology which has predefined levels of QoS which can be
provided to the user [4]. IPv6 has been created as the successor for
IPv4 and resolves issues like the availability of IP addresses and
QoS. This paper provides a design to use the power of WiMAX as an
NSP (Network Service Provider) for NGN using IPv6. The use of the
Traffic Class (TC) field and the Flow Label (FL) field of IPv6 has
been explained for making QoS requests and grants [6], [7]. Using
these fields, the processing time is reduced and routing is simplified.
Also, we define the functioning of the ASN gateway and the NGN
gateway (NGNG) which are edge node interfaces in the NGNWiMAX
design. These gateways ensure QoS management through
built in functions and by certain physical resources and networking
capabilities.
Abstract: Morphogenesis is the process that underpins the selforganised development and regeneration of biological systems. The ability to mimick morphogenesis in artificial systems has great potential for many engineering applications, including production of biological tissue, design of robust electronic systems and the co-ordination of parallel computing. Previous attempts to mimick these complex dynamics within artificial systems have relied upon the use of evolutionary algorithms that have limited their size and complexity. This paper will present some insight into the underlying dynamics of morphogenesis, then show how to, without the assistance of evolutionary algorithms, design cellular architectures that converge to complex patterns.
Abstract: In recent years multi-agent systems have emerged as one of the interesting architectures facilitating distributed collaboration and distributed problem solving. Each node (agent) of the network might pursue its own agenda, exploit its environment, develop its own problem solving strategy and establish required communication strategies. Within each node of the network, one could encounter a diversity of problem-solving approaches. Quite commonly the agents can realize their processing at the level of information granules that is the most suitable from their local points of view. Information granules can come at various levels of granularity. Each agent could exploit a certain formalism of information granulation engaging a machinery of fuzzy sets, interval analysis, rough sets, just to name a few dominant technologies of granular computing. Having this in mind, arises a fundamental issue of forming effective interaction linkages between the agents so that they fully broadcast their findings and benefit from interacting with others.
Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.
Abstract: Business Process Management (BPM) helps in optimizing the business processes inside an enterprise. But BPM architecture does not provide any help for extending the enterprise. Modern business environments and rapidly changing technologies are asking for brisk changes in the business processes. Service Oriented Architecture (SOA) can help in enabling the success of enterprise-wide BPM. SOA supports agility in software development that is directly related to achieve loose coupling of interacting software agents. Agility is a premium concern of the current software designing architectures. Together, BPM and SOA provide a perfect combination for enterprise computing. SOA provides the capabilities for services to be combined together and to support and create an agile, flexible enterprise. But there are still many questions to answer; BPM is better or SOA? and what is the future track of BPM and SOA? This paper tries to answer some of these important questions.
Abstract: Banyan networks are really attractive for serving as
the optical switching architectures due to their unique properties of
small depth and absolute signal loss uniformity. The fact has been
established that the limitations of blocking nature and the nonavailability
of proper connections due to non-rearrangeable property
can be easily ruled out using electro-optic MZI switches as basic
switching elements. Combination of the horizontal expansion and
vertical stacking of optical banyan networks is an appropriate scheme
for constructing non-blocking banyan-based optical switching
networks. The interconnected banyan switching fabrics (IBSF) have
been considered and analyzed to best serve the purpose of optical
switching with electro-optic MZI basic elements. The cross/bar state
interchange for the switches has been facilitated by appropriate
voltage switching or the by the switching of operating wavelength.
The paper is dedicated to the modification of the basic switching
element being used as well as the architecture of the switching
network.
Abstract: The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.
Abstract: With the popularity of the multi-core and many-core architectures there is a great requirement for software frameworks which can support parallel programming methodologies. In this paper we introduce an Eclipse toolkit, JConqurr which is easy to use and provides robust support for flexible parallel progrmaming. JConqurr is a multi-core and many-core programming toolkit for Java which is capable of providing support for common parallel programming patterns which include task, data, divide and conquer and pipeline parallelism. The toolkit uses an annotation and a directive mechanism to convert the sequential code into parallel code. In addition to that we have proposed a novel mechanism to achieve the parallelism using graphical processing units (GPU). Experiments with common parallelizable algorithms have shown that our toolkit can be easily and efficiently used to convert sequential code to parallel code and significant performance gains can be achieved.
Abstract: Optimum communication and performance in
Wireless Sensor Networks, constitute multi-facet challenges due to
the specific networking characteristics as well as the scarce resource
availability. Furthermore, it is becoming increasingly apparent that
isolated layer based approaches often do not meet the demands posed
by WSNs applications due to omission of critical inter-layer
interactions and dependencies. As a counterpart, cross-layer is
receiving high interest aiming to exploit these interactions and
increase network performance. However, in order to clearly identify
existing dependencies, comprehensive performance studies are
required evaluating the effect of different critical network parameters
on system level performance and behavior.This paper-s main
objective is to address the need for multi-parametric performance
evaluations considering critical network parameters using a well
known network simulator, offering useful and practical conclusions
and guidelines. The results reveal strong dependencies among
considered parameters which can be utilized by and drive future
research efforts, towards designing and implementing highly efficient
protocols and architectures.
Abstract: This paper presents software tools that convert the C/Cµ floating point source code for a DSP algorithm into a fixedpoint simulation model that can be used to evaluate the numericalperformance of the algorithm on several different fixed pointplatforms including microprocessors, DSPs and FPGAs. The tools use a novel system for maintaining binary point informationso that the conversion from floating point to fixed point isautomated and the resulting fixed point algorithm achieves maximum possible precision. A configurable architecture is used during the simulation phase so that the algorithm can produce a bit-exact output for several different target devices.
Abstract: The key to the continued success of ANN depends, considerably,
on the use of hybrid structures implemented on cooperative
frame-works. Hybrid architectures provide the ability to the ANN
to validate heterogeneous learning paradigms. This work describes
the implementation of a set of Distributed and Hybrid ANN models
for Character Recognition applied to Anglo-Assamese scripts. The
objective is to describe the effectiveness of Hybrid ANN setups as
innovative means of neural learning for an application like multilingual
handwritten character and numeral recognition.