The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.
[1] I. Sutherland, "Micropipelines," Comm. of ACM, vol. 6, 1989.
[2] Sonics, Incorporated, http://www.sonicsinc.com.
[3] W. Peterson, "Design philosophy of the wishbone SoC architecture,"
1999. Available: http://www.silicore.net/wishbone.htm
[4] D. Flynn, "Amba: enabling reusable on-chip design," Intl. J. IEEE
Micro, pp. 20-27, 1997.
[5] IBMCoreConnect Information, 2000. Available:
http://www.chips.ibm.com/products/powerpc/cors
[6] J. Liang, S. Swaminathan, and R. Tessier, "A SoC: a scalable, singlechip
communications architecture," IEEE Intl. Conf. Parallel
Architectures and Compilation Techniques, pp. 524-529, 2000.
[7] H. Ho, and T.M. Pinkston, "A methodology for designing efficient
on-chip interconnects on well-behaved communication patterns," The
9th Intl. Symposium on High-Performance Computer Architecture
(HPCA-03), pp. 377, 2003.
[8] S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg,
K. Tiensyria, and A. Hemani, "A network on chip architecture and
design methodology," Proc. IEEE Computer Society Annual
Symposium on VLSI, pp. 105-112, 2002.
[9] J. Hu, and R. Marculescu, "Exploiting the routing flexibility for
energy/performance aware mapping of regular NoC architectures,"
Proc. Design, Automation and Test in Europe Conference, 2003.
[10] T.T. Ye, L. Benini, and G.D. MICHELI, "Packetized on-chip
interconnect communication analysis for MPSoC," Proc. Design
Automation and Test in Europe, pp. 344-349, 2003.
[11] W.J. Dally, and B. Towles, "Route packets, not wires: on-chip
interconnection networks," Proc. the 38th Design Automation
Conference, 2001.
[12] L. Peh, and W.J. Dally, "A delay model and speculative architecture
for pipelined routers," 7th Intl. Symp. High-Performance Computer
Architecture (HPCA), 2001.
[13] R. Mullins, A. West, and S. Moore, "Low-latency virtual channel
routers for on-chip network," Proc. 31st Intl. Symp. Computer
Architecture, 2004.
[14] H. Wang, L.S. Peh and S. Malik, "Power driven design of router
microarchitectures in on-chip networks," Proc. MICRO-36, 2003.
[15] E. Rijpkema, K. Goossens et al., "Trade-offs in the design of a router
with both guaranteed and best-effort services for networks on chip,"
IEE Proc.-Comp. Digit. Tech., pp. 294-302, 2003.
[16] L. Benini, G.D. Micheli, "Networks on chips: a new SoC paradigm,"
IEEE Computer, vol. 1, pp. 70-80, 2002.
[17] J. Schmaltz, D. Borrione, "A generic network on chip model,"
Research reports, TIMA Laboratory, Grenoble, France, 2005.
[18] OCP International Partnership. Open Core Protocol Specification. 2.0
Release Candidate, 2003.
[19] N. Banerjee, P. Vellanki and K.S. Chatha, "A power and performance
model for network-on-chip architectures," Proc. DATE, 2004.
[20] P. Vellanki, N. Banerjee and K.S. Chatha, "Quality-of-service and
error control techniques for network-on-chip architectures," Proc.
GLSVLSI-04, Boston, USA, pp. 45-50, 2004.
[21] W.J. Bainbridge, S.B. Fuber, "Chain: a delay insensitive chip area
interconnect," IEEE Micro, vol. 22, pp. 16-23, Sep./Oct. 2002.
[22] Bainbridge, S.B. Fuber, "Asynchronous macrocell interconnect using
marble," International Symposium on Advanced Research in
Asynchronous Circuits and Systems, pp. 122-139, IEEE Press, Avril
1998.
[23] P. Coe, F. Howell, R. Ibbett, and L. Willams, "A hierarchical
computer architecture design and simulation environment," ACM
Transactions on Modelling and Computer Simulation, 8(4), October
1998.
[1] I. Sutherland, "Micropipelines," Comm. of ACM, vol. 6, 1989.
[2] Sonics, Incorporated, http://www.sonicsinc.com.
[3] W. Peterson, "Design philosophy of the wishbone SoC architecture,"
1999. Available: http://www.silicore.net/wishbone.htm
[4] D. Flynn, "Amba: enabling reusable on-chip design," Intl. J. IEEE
Micro, pp. 20-27, 1997.
[5] IBMCoreConnect Information, 2000. Available:
http://www.chips.ibm.com/products/powerpc/cors
[6] J. Liang, S. Swaminathan, and R. Tessier, "A SoC: a scalable, singlechip
communications architecture," IEEE Intl. Conf. Parallel
Architectures and Compilation Techniques, pp. 524-529, 2000.
[7] H. Ho, and T.M. Pinkston, "A methodology for designing efficient
on-chip interconnects on well-behaved communication patterns," The
9th Intl. Symposium on High-Performance Computer Architecture
(HPCA-03), pp. 377, 2003.
[8] S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg,
K. Tiensyria, and A. Hemani, "A network on chip architecture and
design methodology," Proc. IEEE Computer Society Annual
Symposium on VLSI, pp. 105-112, 2002.
[9] J. Hu, and R. Marculescu, "Exploiting the routing flexibility for
energy/performance aware mapping of regular NoC architectures,"
Proc. Design, Automation and Test in Europe Conference, 2003.
[10] T.T. Ye, L. Benini, and G.D. MICHELI, "Packetized on-chip
interconnect communication analysis for MPSoC," Proc. Design
Automation and Test in Europe, pp. 344-349, 2003.
[11] W.J. Dally, and B. Towles, "Route packets, not wires: on-chip
interconnection networks," Proc. the 38th Design Automation
Conference, 2001.
[12] L. Peh, and W.J. Dally, "A delay model and speculative architecture
for pipelined routers," 7th Intl. Symp. High-Performance Computer
Architecture (HPCA), 2001.
[13] R. Mullins, A. West, and S. Moore, "Low-latency virtual channel
routers for on-chip network," Proc. 31st Intl. Symp. Computer
Architecture, 2004.
[14] H. Wang, L.S. Peh and S. Malik, "Power driven design of router
microarchitectures in on-chip networks," Proc. MICRO-36, 2003.
[15] E. Rijpkema, K. Goossens et al., "Trade-offs in the design of a router
with both guaranteed and best-effort services for networks on chip,"
IEE Proc.-Comp. Digit. Tech., pp. 294-302, 2003.
[16] L. Benini, G.D. Micheli, "Networks on chips: a new SoC paradigm,"
IEEE Computer, vol. 1, pp. 70-80, 2002.
[17] J. Schmaltz, D. Borrione, "A generic network on chip model,"
Research reports, TIMA Laboratory, Grenoble, France, 2005.
[18] OCP International Partnership. Open Core Protocol Specification. 2.0
Release Candidate, 2003.
[19] N. Banerjee, P. Vellanki and K.S. Chatha, "A power and performance
model for network-on-chip architectures," Proc. DATE, 2004.
[20] P. Vellanki, N. Banerjee and K.S. Chatha, "Quality-of-service and
error control techniques for network-on-chip architectures," Proc.
GLSVLSI-04, Boston, USA, pp. 45-50, 2004.
[21] W.J. Bainbridge, S.B. Fuber, "Chain: a delay insensitive chip area
interconnect," IEEE Micro, vol. 22, pp. 16-23, Sep./Oct. 2002.
[22] Bainbridge, S.B. Fuber, "Asynchronous macrocell interconnect using
marble," International Symposium on Advanced Research in
Asynchronous Circuits and Systems, pp. 122-139, IEEE Press, Avril
1998.
[23] P. Coe, F. Howell, R. Ibbett, and L. Willams, "A hierarchical
computer architecture design and simulation environment," ACM
Transactions on Modelling and Computer Simulation, 8(4), October
1998.
@article{"International Journal of Electrical, Electronic and Communication Sciences:58982", author = "Abdelkrim Zitouni and Mounir Zid and Sami Badrouchi and Rached Tourki", title = "A Generic and Extensible Spidergon NoC", abstract = "The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.
", keywords = "Dynamic arbiter, Generic router, Spidergon NoC,SoC.", volume = "1", number = "7", pages = "1032-6", }
