Abstract: Border Gateway Protocol (BGP) is the standard routing protocol between various autonomous systems (AS) in the internet. In the event of failure, a considerable delay in the BGP convergence has been shown by empirical measurements. During the convergence time the BGP will repeatedly advertise new routes to some destination and withdraw old ones until it reach a stable state. It has been found that the KEEPALIVE message timer and the HOLD time are tow parameters affecting the convergence speed. This paper aims to find the optimum value for the KEEPALIVE timer and the HOLD time that maximally reduces the convergence time without increasing the traffic. The KEEPALIVE message timer optimal value founded by this paper is 30 second instead of 60 seconds, and the optimal value for the HOLD time is 90 seconds instead of 180 seconds.
Abstract: This paper present a MATLAB-SIMULINK model of a single phase 2.5 KVA, 240V RMS controlled PV VSI (Photovoltaic Voltage Source Inverter) inverter using IGBTs (Insulated Gate Bipolar Transistor). The behavior of output voltage, output current, and the total harmonic distortion (THD), with the variation in input dc blocking capacitor (Cdc), for linear and non-linear load has been analyzed. The values of Cdc as suggested by the other authors in their papers are not clearly defined and it poses difficulty in selecting the proper value. As the dc power stored in Cdc, (generally placed parallel with battery) is used as input to the VSI inverter. The simulation results shows the variation in the output voltage and current with different values of Cdc for linear and non-linear load connected at the output side of PV VSI inverter and suggest the selection of suitable value of Cdc.
Abstract: A high-frequency low-power sinusoidal quadrature
oscillator is presented through the use of two 2nd-order low-pass
current-mirror (CM)-based filters, a 1st-order CM low-pass filter and
a CM bilinear transfer function. The technique is relatively simple
based on (i) inherent time constants of current mirrors, i.e. the
internal capacitances and the transconductance of a diode-connected
NMOS, (ii) a simple negative resistance RN formed by a resistor load
RL of a current mirror. Neither external capacitances nor inductances
are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V
CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature
oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz
and is current-tunable over a range of 370 MHz or 21.6 %. The
power consumption is at approximately 0.45 mW. The amplitude
matching and the quadrature phase matching are better than 0.05 dB
and 0.15°, respectively. Total harmonic distortions (THD) are less
than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise
ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a
normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The
ratio of the oscillation frequency (f0) to the unity-gain frequency (fT)
of a transistor is 0.25. Comparisons to other approaches are also
included.