Abstract: Formal verification is proposed to ensure the
correctness of the design and make functional verification more
efficient. As cache plays a vital role in the design of System on Chip
(SoC), and cache with Memory Management Unit (MMU) and cache
memory unit makes the state space too large for simulation to verify,
then a formal verification is presented for such system design. In the
paper, a formal model checking verification flow is suggested and a
new cache memory model which is called “exhaustive search model”
is proposed. Instead of using large size ram to denote the whole cache
memory, exhaustive search model employs just two cache blocks. For
cache system contains data cache (Dcache) and instruction cache
(Icache), Dcache memory model and Icache memory model are
established separately using the same mechanism. At last, the novel
model is employed to the verification of a cache which is module of a
custom-built SoC system that has been applied in practical, and the
result shows that the cache system is verified correctly using the
exhaustive search model, and it makes the verification much more
manageable and flexible.
Abstract: Design and implementation of a novel B-ACOSD CFAR algorithm is presented in this paper. It is proposed for detecting radar target in log-normal distribution environment. The BACOSD detector is capable to detect automatically the number interference target in the reference cells and detect the real target by an adaptive threshold. The detector is implemented as a System on Chip on FPGA Altera Stratix II using parallelism and pipelining technique. For a reference window of length 16 cells, the experimental results showed that the processor works properly with a processing speed up to 115.13MHz and processing time0.29 ┬Ás, thus meets real-time requirement for a typical radar system.
Abstract: One of the most challengeable issues in ESL
(Electronic System Level) design is the lack of a general modeling
scheme for on chip communication architecture. In this paper some
of the mostly used methodologies for modeling and representation of
on chip communication are investigated. Our goal is studying the
existing methods to extract the requirements of a general
representation scheme for communication architecture synthesis. The
next step, will be introducing a modeling and representation method
for being used in automatically synthesis process of on chip
communication architecture.
Abstract: The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.