Abstract: One of the most challengeable issues in ESL
(Electronic System Level) design is the lack of a general modeling
scheme for on chip communication architecture. In this paper some
of the mostly used methodologies for modeling and representation of
on chip communication are investigated. Our goal is studying the
existing methods to extract the requirements of a general
representation scheme for communication architecture synthesis. The
next step, will be introducing a modeling and representation method
for being used in automatically synthesis process of on chip
communication architecture.