Abstract: In this paper, a few chattering-free Sliding Mode Controllers (SMC) are proposed to stabilize an Active Magnetic Bearing (AMB) system with gyroscopic effect that is proportional to the rotor speed. The improved switching terms of the controller inherited from the saturation-type function and boundary layer control technique is shown to be able to achieve bounded and asymptotic stability, respectively, while the chattering effect in the input is attenuated. This is proven to be advantageous for AMB system since minimization of chattering results in optimized control effort. The performance of each controller is demonstrated via result of simulation in which the measurement of the total consumed energy and maximum control magnitude of each controller illustrates the effectiveness of the proposed controllers.
Abstract: A way of generating millimeter wave I/Q signal using inductive resonator matched poly-phase filter is suggested. Normally the poly-phase filter generates quite accurate I/Q phase and magnitude but the loss of the filter is considerable due to series connection of passive RC components. This loss term directly increases system noise figure when the poly-phase filter is used in RF Front-end. The proposed matching method eliminates above mentioned loss and in addition provides gain on the passive filter. The working algorithm is illustrated by mathematical analysis. The generated I/Q signal is used in implementing millimeter wave phase shifter for the 60 GHz communication system to verify its effectiveness. The circuit is fabricated in 90 nm TSMC RF CMOS process under 1.2 V supply voltage. The measurement results showed that the suggested method improved gain by 6.5 dB and noise by 2.3 dB. The summary of the proposed I/Q generation is compared with previous works.
Abstract: This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.
Abstract: Performance control law is studied for an
interconnected fractional nonlinear system. Applying a backstepping
algorithm, a backstepping sliding mode controller (BSMC) is
developed for fractional nonlinear system. To improve control law
performance, BSMC is coupled to an adaptive sliding mode observer
have a filtered error as a sliding surface. The both architecture
performance is studied throughout the inverted pendulum mounted on
a cart. Simulation result show that the BSMC coupled to an adaptive
sliding mode observer have stable control law and eligible control
amplitude than the BSMC.
Abstract: We present our ongoing work on the development
of a new quadrotor aerial vehicle which has a tilt-wing
mechanism. The vehicle is capable of take-off/landing in vertical flight mode (VTOL) and flying over long distances in horizontal flight mode. Full dynamic model of the vehicle is derived using
Newton-Euler formulation. Linear and nonlinear controllers for
the stabilization of attitude of the vehicle and control of its
altitude have been designed and implemented via simulations. In particular, an LQR controller has been shown to be quite
effective in the vertical flight mode for all possible yaw angles. A sliding mode controller (SMC) with recursive nature has also
been proposed to stabilize the vehicle-s attitude and altitude. Simulation results show that proposed controllers provide
satisfactory performance in achieving desired maneuvers.
Abstract: Transmission control protocol (TCP) Vegas detects
network congestion in the early stage and successfully prevents
periodic packet loss that usually occurs in TCP Reno. It has been
demonstrated that TCP Vegas outperforms TCP Reno in many
aspects. However, TCP Vegas suffers several problems that affect its
congestion avoidance mechanism. One of the most important
weaknesses in TCP Vegas is that alpha and beta depend on a good
expected throughput estimate, which as we have seen, depends on a
good minimum RTT estimate. In order to make the system more
robust alpha and beta must be made responsive to network conditions
(they are currently chosen statically). This paper proposes a modified
Vegas algorithm, which can be adjusted to present good performance
compared to other transmission control protocols (TCPs). In order to
do this, we use PSO algorithm to tune alpha and beta. The simulation
results validate the advantages of the proposed algorithm in term of
performance.
Abstract: This paper proposes a Fuzzy Sliding Mode Control (FSMC) as a control strategy for Buck-Boost DC-DC converter. The proposed fuzzy controller specifies changes in the control signal based on the knowledge of the surface and the surface change to satisfy the sliding mode stability and attraction conditions. The performances of the proposed fuzzy sliding controller are compared to those obtained by a classical sliding mode controller. The satisfactory simulation results show the efficiency of the proposed control law which reduces the chattering phenomenon. Moreover, the obtained results prove the robustness of the proposed control law against variation of the load resistance and the input voltage of the studied converter.
Abstract: This paper presents the optimal design and development
of an axial flux motor for blood pump application. With the design
objective of maximizing the motor efficiency and torque, different
topologies of AFPM machine has been examined. Selection of
optimal magnet fraction, Halbach arrangement of rotor magnets and
the use of Soft Magnetic Composite (SMC) material for the stator
core results in a novel motor with improved efficiency and torque
profile. The results of the 3D Finite element analysis for the novel
motor have been shown.
Abstract: The objective of this paper is to compare the time
specification performance between conventional controller PID and
modern controller SMC for an inverted pendulum system. The goal is
to determine which control strategy delivers better performance with
respect to pendulum-s angle and cart-s position. The inverted
pendulum represents a challenging control problem, which
continually moves toward an uncontrolled state. Two controllers are
presented such as Sliding Mode Control (SMC) and Proportional-
Integral-Derivatives (PID) controllers for controlling the highly
nonlinear system of inverted pendulum model. Simulation study has
been done in Matlab Mfile and simulink environment shows that both
controllers are capable to control multi output inverted pendulum
system successfully. The result shows that Sliding Mode Control
(SMC) produced better response compared to PID control strategies
and the responses are presented in time domain with the details
analysis.
Abstract: This paper deals with the comparison between two proposed control strategies for a DC-DC boost converter. The first control is a classical Sliding Mode Control (SMC) and the second one is a distance based Fuzzy Sliding Mode Control (FSMC). The SMC is an analytical control approach based on the boost mathematical model. However, the FSMC is a non-conventional control approach which does not need the controlled system mathematical model. It needs only the measures of the output voltage to perform the control signal. The obtained simulation results show that the two proposed control methods are robust for the case of load resistance and the input voltage variations. However, the proposed FSMC gives a better step voltage response than the one obtained by the SMC.
Abstract: With the advent of emerging personal computing paradigms such as ubiquitous and mobile computing, Web contents are becoming accessible from a wide range of mobile devices. Since these devices do not have the same rendering capabilities, Web contents need to be adapted for transparent access from a variety of client agents. Such content adaptation is exploited for either an individual element or a set of consecutive elements in a Web document and results in better rendering and faster delivery to the client device. Nevertheless, Web content adaptation sets new challenges for semantic markup. This paper presents an advanced components platform, called SMC, enabling the development of mobility applications and services according to a channel model based on the principles of Services Oriented Architecture (SOA). It then goes on to describe the potential for integration with the Semantic Web through a novel framework of external semantic annotation that prescribes a scheme for representing semantic markup files and a way of associating Web documents with these external annotations. The role of semantic annotation in this framework is to describe the contents of individual documents themselves, assuring the preservation of the semantics during the process of adapting content rendering. Semantic Web content adaptation is a way of adding value to Web contents and facilitates repurposing of Web contents (enhanced browsing, Web Services location and access, etc).
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.
Abstract: This conference paper discusses a risk allocation problem for subprime investing banks involving investment in subprime structured mortgage products (SMPs) and Treasuries. In order to solve this problem, we develop a L'evy process-based model of jump diffusion-type for investment choice in subprime SMPs and Treasuries. This model incorporates subprime SMP losses for which credit default insurance in the form of credit default swaps (CDSs) can be purchased. In essence, we solve a mean swap-at-risk (SaR) optimization problem for investment which determines optimal allocation between SMPs and Treasuries subject to credit risk protection via CDSs. In this regard, SaR is indicative of how much protection investors must purchase from swap protection sellers in order to cover possible losses from SMP default. Here, SaR is defined in terms of value-at-risk (VaR). Finally, we provide an analysis of the aforementioned optimization problem and its connections with the subprime mortgage crisis (SMC).
Abstract: This paper proposes a low-cost reconfigurable
architecture for AES algorithm. The proposed architecture separates
SubBytes and MixColumns into two parallel data path, and supports
different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The
throughput and power consumption can be adjusted by changing the
number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K
Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the
minimum throughput is 114Mbps while only using 1 S-Box
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].