Abstract: One of the most basic functions of control engineers is
tuning of controllers. There are always several process loops in the
plant necessitate of tuning. The auto tuned Proportional Integral
Derivative (PID) Controllers are designed for applications where
large load changes are expected or the need for extreme accuracy and
fast response time exists. The algorithm presented in this paper is
used for the tuning PID controller to obtain its parameters with a
minimum computing complexity. It requires continuous analysis of
variation in few parameters, and let the program to do the plant test
and calculate the controller parameters to adjust and optimize the
variables for the best performance. The algorithm developed needs
less time as compared to a normal step response test for continuous
tuning of the PID through gain scheduling.
Abstract: In biological and biomedical research motif finding tools are important in locating regulatory elements in DNA sequences. There are many such motif finding tools available, which often yield position weight matrices and significance indicators. These indicators, p-values and E-values, describe the likelihood that a motif alignment is generated by the background process, and the expected number of occurrences of the motif in the data set, respectively. The various tools often estimate these indicators differently, making them not directly comparable. One approach for comparing motifs from different tools, is computing the E-value as the product of the p-value and the number of possible alignments in the data set. In this paper we explore the combinatorics of the motif alignment models OOPS, ZOOPS, and ANR, and propose a generic algorithm for computing the number of possible combinations accurately. We also show that using the wrong alignment model can give E-values that significantly diverge from their true values.
Abstract: Fatigue behaviors of Lead Zirconate Titanate (PZT)
ceramics under different amplitude of bipolar electrical loads have
been investigated. Fatigue behavior is represented by the change of
hysteresis loops and remnant polarization. Three levels of electrical
load amplitudes (1.00, 1.25 and 1.50 kV /mm) were applied in this
experimental. It was found that the remnant polarization decreased
significantly with the number of loading cycles. The degree of fatigue
degradation depends on the amplitude of electric field. The higher
amplitude exhibits the greater fatigue degradation.
Abstract: The paper deals with the perspectives and possibilities
of "smart solutions" to critical infrastructure protection. It means that
common computer aided technologies are used from the perspective
of new, better protection of selected infrastructure objects. The paper
is focused on the co-product of the Czech Defence Research Project -
ADAPTIV. This project is carrying out by the University of Defence,
Faculty of Economics and Management at the Department of Civil
Protection. The project creates system and technology for adaptive
cybernetic camouflage of armed forces objects, armaments, vehicles
and troops and of mobilization infrastructure. These adaptive
camouflage system and technology will be useful for army tactic
activities protection and for decoys generation also. The fourth
chapter of the paper concerns the possibilities of using the introduced
technology to the protection of selected civil (economically
important), critical infrastructure objects. The aim of this section
is to introduce the scientific capabilities and potential of the
University of Defence research results and solutions for the practice.
Abstract: Repetitive control and feedback dithering modulation
are applied to a single-phase voltage source inverter, with an aim to
eliminate harmonics and stabilize the inverter under load variations.
The proposed control and modulation scheme comprise multiple loops
of feedback, which helps improve inverter performance and
robustness. Experimental results show that the designed inverter
exhibits very low distortion at its output with THD of about 0.3%
under different load variations.
Abstract: This paper proposes a new technique for improving
the efficiency of software testing, which is based on a conventional
attempt to reduce test cases that have to be tested for any given
software. The approach utilizes the advantage of Regression Testing
where fewer test cases would lessen time consumption of the testing
as a whole. The technique also offers a means to perform test case
generation automatically. Compared to one of the techniques in the
literature where the tester has no option but to perform the test case
generation manually, the proposed technique provides a better
option. As for the test cases reduction, the technique uses simple
algebraic conditions to assign fixed values to variables (Maximum,
minimum and constant variables). By doing this, the variables values
would be limited within a definite range, resulting in fewer numbers
of possible test cases to process. The technique can also be used in
program loops and arrays.
Abstract: This paper presents a novel approach for optimal
reconfiguration of radial distribution systems. Optimal
reconfiguration involves the selection of the best set of branches to
be opened, one each from each loop, such that the resulting radial
distribution system gets the desired performance. In this paper an
algorithm is proposed based on simple heuristic rules and identified
an effective switch status configuration of distribution system for the
minimum loss reduction. This proposed algorithm consists of two
parts; one is to determine the best switching combinations in all loops
with minimum computational effort and the other is simple optimum
power loss calculation of the best switching combination found in
part one by load flows. To demonstrate the validity of the proposed
algorithm, computer simulations are carried out on 33-bus system.
The results show that the performance of the proposed method is
better than that of the other methods.
Abstract: Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.
Abstract: Un-doped GaN film of thickness 1.90 mm, grown on
sapphire substrate were uniformly implanted with 325 keV Mn+ ions
for various fluences varying from 1.75 x 1015 - 2.0 x 1016 ions cm-2 at
3500 C substrate temperature. The structural, morphological and
magnetic properties of Mn ion implanted gallium nitride samples
were studied using XRD, AFM and SQUID techniques. XRD of the
sample implanted with various ion fluences showed the presence of
different magnetic phases of Ga3Mn, Ga0.6Mn0.4 and Mn4N.
However, the compositions of these phases were found to be
depended on the ion fluence. AFM images of non-implanted sample
showed micrograph with rms surface roughness 2.17 nm. Whereas
samples implanted with the various fluences showed the presence of
nano clusters on the surface of GaN. The shape, size and density of
the clusters were found to vary with respect to ion fluence. Magnetic
moment versus applied field curves of the samples implanted with
various fluences exhibit the hysteresis loops. The Curie temperature
estimated from zero field cooled and field cooled curves for the
samples implanted with the fluence of 1.75 x 1015, 1.5 x 1016 and 2.0
x 1016 ions cm-2 was found to be 309 K, 342 K and 350 K
respectively.
Abstract: Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.
Abstract: In this paper we will consider the most known ratios
control schemes ((L/D, V/B),(L/D,V/F), Ryskamp-s, and
(D/(L+D),V/B)) for binary distillation column and we compare them
in the basis of interactions and disturbance propagation. The models
for these configurations are deuced using mathematical
transformations taking the energy balance structure (LV) as a base
model. The dynamic relative magnitude criterion (DRMC) is used to
assess the interactions. The results show that the introduction of
ratios in controlling the column tends to minimize the degree of
interactions between the loops.
Abstract: The Boundary Representation of a 3D manifold contains
FACES (connected subsets of a parametric surface S : R2 -!
R3). In many science and engineering applications it is cumbersome
and algebraically difficult to deal with the polynomial set and
constraints (LOOPs) representing the FACE. Because of this reason, a
Piecewise Linear (PL) approximation of the FACE is needed, which is
usually represented in terms of triangles (i.e. 2-simplices). Solving the
problem of FACE triangulation requires producing quality triangles
which are: (i) independent of the arguments of S, (ii) sensitive to the
local curvatures, and (iii) compliant with the boundaries of the FACE
and (iv) topologically compatible with the triangles of the neighboring
FACEs. In the existing literature there are no guarantees for the point
(iii). This article contributes to the topic of triangulations conforming
to the boundaries of the FACE by applying the concept of parameterindependent
Gabriel complex, which improves the correctness of the
triangulation regarding aspects (iii) and (iv). In addition, the article
applies the geometric concept of tangent ball to a surface at a point to
address points (i) and (ii). Additional research is needed in algorithms
that (i) take advantage of the concepts presented in the heuristic
algorithm proposed and (ii) can be proved correct.
Abstract: This paper provides the design steps of a robust Linear
Matrix Inequality (LMI) based iterative multivariable PID controller
whose duty is to drive a sample power system that comprises a
synchronous generator connected to a large network via a step-up
transformer and a transmission line. The generator is equipped with
two control-loops, namely, the speed/power (governor) and voltage
(exciter). Both loops are lumped in one where the error in the
terminal voltage and output active power represent the controller
inputs and the generator-exciter voltage and governor-valve position
represent its outputs. Multivariable PID is considered here because of
its wide use in the industry, simple structure and easy
implementation. It is also preferred in plants of higher order that
cannot be reduced to lower ones. To improve its robustness to
variation in the controlled variables, H∞-norm of the system transfer
function is used. To show the effectiveness of the controller, divers
tests, namely, step/tracking in the controlled variables, and variation
in plant parameters, are applied. A comparative study between the
proposed controller and a robust H∞ LMI-based output feedback is
given by its robustness to disturbance rejection. From the simulation
results, the iterative multivariable PID shows superiority.
Abstract: Quality of Service (QoS) Routing aims to find path between source and destination satisfying the QoS requirements which efficiently using the network resources and underlying routing algorithm and to fmd low-cost paths that satisfy given QoS constraints. One of the key issues in providing end-to-end QoS guarantees in packet networks is determining feasible path that satisfies a number of QoS constraints. We present a Optimized Multi- Constrained Routing (OMCR) algorithm for the computation of constrained paths for QoS routing in computer networks. OMCR applies distance vector to construct a shortest path for each destination with reference to a given optimization metric, from which a set of feasible paths are derived at each node. OMCR is able to fmd feasible paths as well as optimize the utilization of network resources. OMCR operates with the hop-by-hop, connectionless routing model in IP Internet and does not create any loops while fmding the feasible paths. Nodes running OMCR not necessarily maintaining global view of network state such as topology, resource information and routing updates are sent only to neighboring nodes whereas its counterpart link-state routing method depend on complete network state for constrained path computation and that incurs excessive communication overhead.
Abstract: This paper presents the mathematical model and
control strategy on DQ frame of shunt active power filter. The
structure of the shunt active power filter is the voltage source inverter
(VSI). The pulse width modulation (PWM) with PI controller is used
in the paper. The concept of DQ frame to apply with the shunt active
power filter is described. Moreover, the detail of the PI controller
design for two current loops and one voltage loop are fully explained.
The DQ axis with Fourier (DQF) method is applied to calculate the
reference currents on DQ frame. The simulation results show that the
control strategy and the design method presented in the paper can
provide the good performance of the shunt active power filter.
Moreover, the %THD of the source currents after compensation can
follow the IEEE Std.519-1992.
Abstract: A new algorithm called Character-Comparison to Character-Access (CCCA) is developed to test the effect of both: 1) converting character-comparison and number-comparison into character-access and 2) the starting point of checking on the performance of the checking operation in string searching. An experiment is performed using both English text and DNA text with different sizes. The results are compared with five algorithms, namely, Naive, BM, Inf_Suf_Pref, Raita, and Cycle. With the CCCA algorithm, the results suggest that the evaluation criteria of the average number of total comparisons are improved up to 35%. Furthermore, the results suggest that the clock time required by the other algorithms is improved in range from 22.13% to 42.33% by the new CCCA algorithm.
Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.