Abstract: IPsec has now become a standard information security
technology throughout the Internet society. It provides a well-defined
architecture that takes into account confidentiality, authentication,
integrity, secure key exchange and protection mechanism against
replay attack also. For the connectionless security services on packet
basis, IETF IPsec Working Group has standardized two extension
headers (AH&ESP), key exchange and authentication protocols. It is
also working on lightweight key exchange protocol and MIB's for
security management. IPsec technology has been implemented on
various platforms in IPv4 and IPv6, gradually replacing old
application-specific security mechanisms. IPv4 and IPv6 are not
directly compatible, so programs and systems designed to one
standard can not communicate with those designed to the other. We
propose the design and implementation of controlled Internet security
system, which is IPsec-based Internet information security system in
IPv4/IPv6 network and also we show the data of performance
measurement. With the features like improved scalability and
routing, security, ease-of-configuration, and higher performance of
IPv6, the controlled Internet security system provides consistent
security policy and integrated security management on IPsec-based
Internet security system.
Abstract: Enterprise Architecture (EA) is a framework for description, coordination and alignment of all activities across the organization in order to achieve strategic goals using ICT enablers. A number of EA-compatible frameworks have been developed. We, in this paper, mainly focus on Federal Enterprise Architecture Framework (FEAF) since its reference models are plentiful. Among these models we are interested here in its business reference model (BRM). The test process is one important subject of an EA project which is to somewhat overlooked. This lack of attention may cause drawbacks or even failure of an enterprise architecture project. To address this issue we intend to use International Software Testing Qualification Board (ISTQB) framework and standard test suites to present a method to improve EA testing process. The main challenge is how to communicate between the concepts of EA and ISTQB. In this paper, we propose a method for integrating these concepts.
Abstract: Two species of Physalis, P.angulataL. and P.
peruviana L. were used as models for comparative study to
understand the values of micro-morphological, -anatomical and
architectural characteristics of leaf for taxonomic purposes and
possibly breeding and commercial applications. Both speciespossess
amphistomaticleaves with 1-layer epidermis, 3-4-layer spongy
mesophyll andbicollateral bundle midrib. Palisade parenchyma cells
of P. angulatawere almost twice longer (65-75 μm) than the other
one. Type of stomata was similar as anomocyticbut stomatal
index(SI) at adaxial surface and abaxial surface of P. angulata were
less than of P. peruvianaas 3.57, 4.00 and6.25, 6.66 respectively.
Some leaf architectural characteristics such as leaf shape, order of
venationalsoprovided information of taxonomic significance
Abstract: The concerns of education and practice of architecture
do not necessarily overlap. Indeed the gap between them could be
seen increasingly and less frequently bridged. We suggest that
changing in architecture education and clarifying the relationship
between these two can help to find and address the opportunities and
unique positions to bridge this gulf.
Abstract: Business Process Management (BPM) helps in optimizing the business processes inside an enterprise. But BPM architecture does not provide any help for extending the enterprise. Modern business environments and rapidly changing technologies are asking for brisk changes in the business processes. Service Oriented Architecture (SOA) can help in enabling the success of enterprise-wide BPM. SOA supports agility in software development that is directly related to achieve loose coupling of interacting software agents. Agility is a premium concern of the current software designing architectures. Together, BPM and SOA provide a perfect combination for enterprise computing. SOA provides the capabilities for services to be combined together and to support and create an agile, flexible enterprise. But there are still many questions to answer; BPM is better or SOA? and what is the future track of BPM and SOA? This paper tries to answer some of these important questions.
Abstract: Banyan networks are really attractive for serving as
the optical switching architectures due to their unique properties of
small depth and absolute signal loss uniformity. The fact has been
established that the limitations of blocking nature and the nonavailability
of proper connections due to non-rearrangeable property
can be easily ruled out using electro-optic MZI switches as basic
switching elements. Combination of the horizontal expansion and
vertical stacking of optical banyan networks is an appropriate scheme
for constructing non-blocking banyan-based optical switching
networks. The interconnected banyan switching fabrics (IBSF) have
been considered and analyzed to best serve the purpose of optical
switching with electro-optic MZI basic elements. The cross/bar state
interchange for the switches has been facilitated by appropriate
voltage switching or the by the switching of operating wavelength.
The paper is dedicated to the modification of the basic switching
element being used as well as the architecture of the switching
network.
Abstract: The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.
Abstract: A Simultaneous Multithreading (SMT) Processor is
capable of executing instructions from multiple threads in the same
cycle. SMT in fact was introduced as a powerful architecture to
superscalar to increase the throughput of the processor.
Simultaneous Multithreading is a technique that permits multiple
instructions from multiple independent applications or threads to
compete limited resources each cycle. While the fetch unit has been
identified as one of the major bottlenecks of SMT architecture, several
fetch schemes were proposed by prior works to enhance the fetching
efficiency and overall performance.
In this paper, we propose a novel fetch policy called queue situation
identifier (QSI) which counts some kind of long latency instructions of
each thread each cycle then properly selects which threads to fetch
next cycle. Simulation results show that in best case our fetch policy
can achieve 30% on speedup and also can reduce the data cache level 1
miss rate.
Abstract: This paper presents the hardware design of a unified
architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional
(2-D) transform for the HEVC standard. This
architecture is based on fast integer transform algorithms. It is
designed only with adders and shifts in order to reduce the hardware
cost significantly. The goal is to ensure the maximum circuit reuse
during the computing while saving 40% for the number of operations.
The architecture is developed using FIFOs to compute the second
dimension. The proposed hardware was implemented in VHDL. The
VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA.
The number of cycles in this architecture varies from 33 in 4-point-
2D-DCT to 172 when the 16-point-2D-DCT is computed. Results
show frequency improvements reaching 96% when compared to an
architecture described as the direct transcription of the algorithm.
Abstract: With the popularity of the multi-core and many-core architectures there is a great requirement for software frameworks which can support parallel programming methodologies. In this paper we introduce an Eclipse toolkit, JConqurr which is easy to use and provides robust support for flexible parallel progrmaming. JConqurr is a multi-core and many-core programming toolkit for Java which is capable of providing support for common parallel programming patterns which include task, data, divide and conquer and pipeline parallelism. The toolkit uses an annotation and a directive mechanism to convert the sequential code into parallel code. In addition to that we have proposed a novel mechanism to achieve the parallelism using graphical processing units (GPU). Experiments with common parallelizable algorithms have shown that our toolkit can be easily and efficiently used to convert sequential code to parallel code and significant performance gains can be achieved.
Abstract: Optimum communication and performance in
Wireless Sensor Networks, constitute multi-facet challenges due to
the specific networking characteristics as well as the scarce resource
availability. Furthermore, it is becoming increasingly apparent that
isolated layer based approaches often do not meet the demands posed
by WSNs applications due to omission of critical inter-layer
interactions and dependencies. As a counterpart, cross-layer is
receiving high interest aiming to exploit these interactions and
increase network performance. However, in order to clearly identify
existing dependencies, comprehensive performance studies are
required evaluating the effect of different critical network parameters
on system level performance and behavior.This paper-s main
objective is to address the need for multi-parametric performance
evaluations considering critical network parameters using a well
known network simulator, offering useful and practical conclusions
and guidelines. The results reveal strong dependencies among
considered parameters which can be utilized by and drive future
research efforts, towards designing and implementing highly efficient
protocols and architectures.
Abstract: The birdhouses and dovecotes, which are the indicator
of naturalness and human-animal relationship, are one of the
traditional cultural values of Turkey. With their structures compatible
with nature and respectful to humans the bird houses and dovecotes,
which have an important position in local urbanization models as a
representative of the civil architecture with their unique form and
function are important subjects that should be evaluated in a wide
frame comprising from architecture to urbanism, from ecologic
agriculture to globalization. The traditional bird houses and
dovecotes are disregarded due to the insensitivity affecting the city
life and the change in the public sense of art. In this study, the
characteristic properties of traditional dovecotes and birdhouses,
started in 13th century and ended in 19th century in Anatolia, are
tried to be defined for the sustainability of the tradition and for giving
a new direction to the designers.
Abstract: This paper presents software tools that convert the C/Cµ floating point source code for a DSP algorithm into a fixedpoint simulation model that can be used to evaluate the numericalperformance of the algorithm on several different fixed pointplatforms including microprocessors, DSPs and FPGAs. The tools use a novel system for maintaining binary point informationso that the conversion from floating point to fixed point isautomated and the resulting fixed point algorithm achieves maximum possible precision. A configurable architecture is used during the simulation phase so that the algorithm can produce a bit-exact output for several different target devices.
Abstract: In H.264/AVC video encoding, rate-distortion
optimization for mode selection plays a significant role to achieve
outstanding performance in compression efficiency and video quality.
However, this mode selection process also makes the encoding
process extremely complex, especially in the computation of the ratedistortion
cost function, which includes the computations of the sum
of squared difference (SSD) between the original and reconstructed
image blocks and context-based entropy coding of the block. In this
paper, a transform-domain rate-distortion optimization accelerator
based on fast SSD (FSSD) and VLC-based rate estimation algorithm
is proposed. This algorithm could significantly simplify the hardware
architecture for the rate-distortion cost computation with only
ignorable performance degradation. An efficient hardware structure
for implementing the proposed transform-domain rate-distortion
optimization accelerator is also proposed. Simulation results
demonstrated that the proposed algorithm reduces about 47% of total
encoding time with negligible degradation of coding performance.
The proposed method can be easily applied to many mobile video
application areas such as a digital camera and a DMB (Digital
Multimedia Broadcasting) phone.
Abstract: Wireless LAN technologies have picked up
momentum in the recent years due to their ease of deployment, cost
and availability. The era of wireless LAN has also given rise to
unique applications like VOIP, IPTV and unified messaging.
However, these real-time applications are very sensitive to network
and handoff latencies. To successfully support these applications,
seamless roaming during the movement of mobile station has become
crucial. Nowadays, centralized architecture models support roaming
in WLANs. They have the ability to manage, control and
troubleshoot large scale WLAN deployments. This model is managed
by Control and Provision of Wireless Access Point protocol
(CAPWAP). This paper covers the CAPWAP architectural solution
along with its proposals that have emerged. Based on the literature
survey conducted in this paper, we found that the proposed
algorithms to reduce roaming latency in CAPWAP architecture do
not support seamless roaming. Additionally, they are not sufficient
during the initial period of the network. This paper also suggests
important design consideration for mobility support in future
centralized IEEE 802.11 networks.
Abstract: I/O workload is a critical and important factor to
analyze I/O pattern and file system performance. However tracing I/O
operations on the fly distributed parallel file system is non-trivial due
to collection overhead and a large volume of data. In this paper, we
design and implement a parallel file system logging method for high
performance computing using shared memory-based multi-layer
scheme. It minimizes the overhead with reduced logging operation
response time and provides efficient post-processing scheme through
shared memory. Separated logging server can collect sequential logs
from multiple clients in a cluster through packet communication.
Implementation and evaluation result shows low overhead and high
scalability of this architecture for high performance parallel logging
analysis.
Abstract: In online context, the design and implementation of
effective remote laboratories environment is highly challenging on
account of hardware and software needs. This paper presents the
remote laboratory software framework modified from ilab shared
architecture (ISA). The ISA is a framework which enables students to
remotely acccess and control experimental hardware using internet
infrastructure. The need for remote laboratories came after
experiencing problems imposed by traditional laboratories. Among
them are: the high cost of laboratory equipment, scarcity of space,
scarcity of technical personnel along with the restricted university
budget creates a significant bottleneck on building required
laboratory experiments. The solution to these problems is to build
web-accessible laboratories. Remote laboratories allow students and
educators to interact with real laboratory equipment located
anywhere in the world at anytime. Recently, many universities and
other educational institutions especially in third world countries rely
on simulations because they do not afford the experimental
equipment they require to their students. Remote laboratories enable
users to get real data from real-time hand-on experiments. To
implement many remote laboratories, the system architecture should
be flexible, understandable and easy to implement, so that different
laboratories with different hardware can be deployed easily. The
modifications were made to enable developers to add more
equipment in ISA framework and to attract the new developers to
develop many online laboratories.
Abstract: Software maintenance is extremely important activity in software development life cycle. It involves a lot of human efforts, cost and time. Software maintenance may be further subdivided into different activities such as fault prediction, fault detection, fault prevention, fault correction etc. This topic has gained substantial attention due to sophisticated and complex applications, commercial hardware, clustered architecture and artificial intelligence. In this paper we surveyed the work done in the field of software maintenance. Software fault prediction has been studied in context of fault prone modules, self healing systems, developer information, maintenance models etc. Still a lot of things like modeling and weightage of impact of different kind of faults in the various types of software systems need to be explored in the field of fault severity.
Abstract: Music Information Retrieval (MIR) and modern data mining techniques are applied to identify style markers in midi music for stylometric analysis and author attribution. Over 100 attributes are extracted from a library of 2830 songs then mined using supervised learning data mining techniques. Two attributes are identified that provide high informational gain. These attributes are then used as style markers to predict authorship. Using these style markers the authors are able to correctly distinguish songs written by the Beatles from those that were not with a precision and accuracy of over 98 per cent. The identification of these style markers as well as the architecture for this research provides a foundation for future research in musical stylometry.
Abstract: Open Agent System platform based on High Level
Architecture is firstly proposed to support the application involving
heterogeneous agents. The basic idea is to develop different wrappers
for different agent systems, which are wrapped as federates to join a
federation. The platform is based on High Level Architecture and the
advantages for this open standard are naturally inherited, such as
system interoperability and reuse. Especially, the federal architecture
allows different federates to be heterogeneous so as to support the
integration of different agent systems. Furthermore, both implicit
communication and explicit communication between agents can be
supported. Then, as the wrapper RTI_JADE an example, the
components are discussed. Finally, the performance of RTI_JADE is
analyzed. The results show that RTI_JADE works very efficiently.