Abstract: Since Network-on-Chip (NoC) uses network
interfaces (NIs) to improve the design productivity, by now, there
have been a few papers addressing the design and implementation of a
NI module. However, none of them considered the difference of
address encoding methods between NoC and the traditional
bus-shared architecture. On the basis of this difference, in the paper,
we introduce a transmit mechanism to solve such a problem for global
asynchronous locally synchronous (GALS) NoC. Furthermore, we
give the concrete implementation of the NI module in this transmit
mechanism. Finally, we evaluate its performance and area overhead
by a VHDL-based cycle-accurate RTL model and simulation results
confirm the validity of this address-oriented transmit mechanism.
Abstract: Elastic boundary eigensolution problems are converted
into boundary integral equations by potential theory. The kernels of
the boundary integral equations have both the logarithmic and Hilbert
singularity simultaneously. We present the mechanical quadrature
methods for solving eigensolutions of the boundary integral equations
by dealing with two kinds of singularities at the same time. The methods
possess high accuracy O(h3) and low computing complexity. The
convergence and stability are proved based on Anselone-s collective
compact theory. Bases on the asymptotic error expansion with odd
powers, we can greatly improve the accuracy of the approximation,
and also derive a posteriori error estimate which can be used for
constructing self-adaptive algorithms. The efficiency of the algorithms
are illustrated by numerical examples.
Abstract: Network on Chip (NoC) has emerged as a promising
on chip communication infrastructure. Three Dimensional Integrate
Circuit (3D IC) provides small interconnection length between layers
and the interconnect scalability in the third dimension, which can
further improve the performance of NoC. Therefore, in this paper,
a hierarchical cluster-based interconnect architecture is merged with
the 3D IC. This interconnect architecture significantly reduces the
number of long wires. Since this architecture only has approximately
a quarter of routers in 3D mesh-based architecture, the average
number of hops is smaller, which leads to lower latency and higher
throughput. Moreover, smaller number of routers decreases the area
overhead. Meanwhile, some dual links are inserted into the bottlenecks
of communication to improve the performance of NoC.
Simulation results demonstrate our theoretical analysis and show the
advantages of our proposed architecture in latency, throughput and
area, when compared with 3D mesh-based architecture.
Abstract: In this paper, we research the standard 13-point difference schemes for solving the biharmonic equation. Heuristic method is applied to judging the stability of multi-level difference schemes of the biharmonic equation. It is showed that the standard 13-point difference schemes are stable.