Abstract: We integrate TiN/Ni/HfO2/Si RRAM cell with a
vertical gate-all-around (GAA) nanowire transistor to achieve
compact 4F2 footprint in a 1T1R configuration. The tip of the Si
nanowire (source of the transistor) serves as bottom electrode of the
memory cell. Fabricated devices with nanowire diameter ~ 50nm
demonstrate ultra-low current/power switching; unipolar switching
with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching
with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the
switching current is found to scale with nanowire diameter making the
architecture promising for future scaling.
Abstract: In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.