Abstract: Logarithms reduce products to sums and powers to products; they play an important role in signal processing, communication and information theory. They are primarily
used for hardware calculations, handling multiplications, divisions,
powers, and roots effectively. There are three commonly
used bases for logarithms; the logarithm with base-10 is called
the common logarithm, the natural logarithm with base-e and
the binary logarithm with base-2. This paper demonstrates different
methods of calculation for log2 showing the complexity
of each and finds out the most accurate and efficient besides
giving insights to their hardware design. We present a new
method called Floor Shift for fast calculation of log2, and
then we combine this algorithm with Taylor series to improve
the accuracy of the output, we illustrate that by using two
examples. We finally compare the algorithms and conclude
with our remarks.
Abstract: Scheduling algorithm is a key technology in satellite
switching system with input-buffer. In this paper, a new scheduling
algorithm and its realization are proposed. Based on Crossbar
switching fabric, the algorithm adopts serial scheduling strategy and
adjusts the output port arbitrating strategy for the better equity of every
port. Consequently, it increases the matching probability. The
algorithm can greatly reduce the scheduling delay and cell loss rate.
The analysis and simulation results by OPNET show that the proposed
algorithm has the better performance than others in average delay and
cell loss rate, and has the equivalent complexity. On the basis of these
results, the hardware realization and simulation based on FPGA are
completed, which validate the feasibility of the new scheduling
algorithm.
Abstract: Model-checking tools such as Symbolic Model Verifier
(SMV) and NuSMV are available for checking hardware designs.
These tools can automatically check the formal legitimacy of a
design. However, NuSMV is too low level for describing a complete
hardware design. It is therefore necessary to translate the system
definition, as designed in a language such as Verilog or VHDL, into
a language such as NuSMV for validation. In this paper, we present
a meta hardware description language, Melasy, that contains a code
generator for existing hardware description languages (HDLs) and
languages for model checking that solve this problem.
Abstract: This paper presents a dynamic adaptation scheme for
the frequency of inter-deme migration in distributed genetic algorithms
(GA), and its VLSI hardware design. Distributed GA,
or multi-deme-based GA, uses multiple populations which evolve
concurrently. The purpose of dynamic adaptation is to improve
convergence performance so as to obtain better solutions. Through
simulation experiments, we proved that our scheme achieves better
performance than fixed frequency migration schemes.