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The Methodology of Flip Chip Using Astro Place and Route Tool

Year: 2013 Volume: 7 Issue: 12 1572 - 1575 Pages

Abstract: This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Utilization of Agro-Industrial Waste in Metal Matrix Composites: Towards Sustainability

Year: 2013 Volume: 7 Issue: 1 25 - 33 Pages

Abstract: The application of agro-industrial waste in Aluminum Metal Matrix Composites has been getting more attention as they can reinforce particles in metal matrix which enhance the strength properties of the composites. In addition, by applying these agroindustrial wastes in useful way not only save the manufacturing cost of products but also reduce the pollutions on environment. This paper represents a literature review on a range of industrial wastes and their utilization in metal matrix composites. The paper describes the synthesis methods of agro-industrial waste filled metal matrix composite materials and their mechanical, wear, corrosion, and physical properties. It also highlights the current application and future potential of agro-industrial waste reinforced composites in aerospace, automotive and other construction industries.

Effect of Curing Profile to Eliminate the Voids / Black Dots Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

Year: 2009 Volume: 3 Issue: 11 2014 - 2019 Pages

Abstract: Void formation in underfill is considered as failure in flip chip manufacturing process. Void formation possibly caused by several factors such as poor soldering and flux residue during die attach process, void entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the comparison of single step and two steps curing profile towards the void and black dots formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). Statistic analysis was conducted to analyze how different factors such as wafer lot, sawing technique, underfill fillet height and curing profile recipe were affected the formation of voids and black dots. A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids and black dots. It was shown that the 2 steps curing profile provided solution for void elimination and black dots in underfill after curing process.