Abstract: This paper presents the 20-GHz fractional PLL (Phase
Locked Loop) circuit for the next generation Wi-Fi by using 90 nm
TSMC process. The newly suggested millimeter wave 16/17
pre-scalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 % of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4-bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4-bit varactor bank. The measured operational bandwidth is 18.2
~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of
-58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
Abstract: The aim of this paper is to emphasize and alleviate the effect of phase noise due to imperfect local oscillators on the performances of a Multi-Carrier CDMA system. After the cancellation of Common Phase Error (CPE), an iterative approach is introduced which iteratively estimates Inter-Carrier Interference (ICI) components in the frequency domain and cancels their contribution in the time domain. Simulation are conducted in order to investigate the achievable performances for several parameters, such as the spreading factor, the modulation order, the phase noise power and the transmission Signal-to-Noise Ratio.