Abstract: Treating data based on its location in memory has received much attention in recent years due to its different properties, which offer important aspects for cache utilization. Stack data and non-stack data may interfere with each other’s locality in the data cache. One of the important aspects of stack data is that it has high spatial and temporal locality. In this work, we simulate non-unified cache design that split data cache into stack and non-stack caches in order to maintain stack data and non-stack data separate in different caches. We observe that the overall hit rate of non-unified cache design is sensitive to the size of non-stack cache. Then, we investigate the appropriate size and associativity for stack cache to achieve high hit ratio especially when over 99% of accesses are directed to stack cache. The result shows that on average more than 99% of stack cache accuracy is achieved by using 2KB of capacity and 1-way associativity. Further, we analyze the improvement in hit rate when adding small, fixed, size of stack cache at level1 to unified cache architecture. The result shows that the overall hit rate of unified cache design with adding 1KB of stack cache is improved by approximately, on average, 3.9% for Rijndael benchmark. The stack cache is simulated by using SimpleScalar toolset.
Abstract: In this paper, an efficient technique is proposed to manage the cache memory. The proposed technique introduces some modifications on the well-known set associative mapping technique. This modification requires a little alteration in the structure of the cache memory and on the way by which it can be referenced. The proposed alteration leads to increase the set size virtually and consequently to improve the performance and the utilization of the cache memory. The current mapping techniques have accomplished good results. In fact, there are still different cases in which cache memory lines are left empty and not used, whereas two or more processes overwrite the lines of each other, instead of using those empty lines. The proposed algorithm aims at finding an efficient way to deal with such problem.
Abstract: Wireless sensor networks (WSNs) have gained
tremendous attention in recent years due to their numerous
applications. Due to the limited energy resource, energy efficient
operation of sensor nodes is a key issue in wireless sensor networks.
Cooperative caching which ensures sharing of data among various
nodes reduces the number of communications over the wireless
channels and thus enhances the overall lifetime of a wireless sensor
network. In this paper, we propose a cooperative caching scheme
called ZCS (Zone Cooperation at Sensors) for wireless sensor
networks. In ZCS scheme, one-hop neighbors of a sensor node form a
cooperative cache zone and share the cached data with each other.
Simulation experiments show that the ZCS caching scheme achieves
significant improvements in byte hit ratio and average query latency
in comparison with other caching strategies.
Abstract: A high performance computer includes a fast
processor and millions bytes of memory. During the data processing,
huge amount of information are shuffled between the memory and
processor. Because of its small size and its effectiveness speed, cache
has become a common feature of high performance computers.
Enhancing cache performance proved to be essential in the speed up
of cache-based computers. Most enhancement approaches can be
classified as either software based or hardware controlled. The
performance of the cache is quantified in terms of hit ratio or miss
ratio. In this paper, we are optimizing the cache performance based
on enhancing the cache hit ratio. The optimum cache performance is
obtained by focusing on the cache hardware modification in the way
to make a quick rejection to the missed line's tags from the hit-or
miss comparison stage, and thus a low hit time for the wanted line in
the cache is achieved. In the proposed technique which we called
Even- Odd Tabulation (EOT), the cache lines come from the main
memory into cache are classified in two types; even line's tags and
odd line's tags depending on their Least Significant Bit (LSB). This
division is exploited by EOT technique to reject the miss match line's
tags in very low time compared to the time spent by the main
comparator in the cache, giving an optimum hitting time for the
wanted cache line. The high performance of EOT technique against
the familiar mapping technique FAM is shown in the simulated
results.
Abstract: Block replacement algorithms to increase hit ratio
have been extensively used in cache memory management. Among
basic replacement schemes, LRU and FIFO have been shown to be
effective replacement algorithms in terms of hit rates. In this paper,
we introduce a flexible stack-based circuit which can be employed in
hardware implementation of both LRU and FIFO policies. We
propose a simple and efficient architecture such that stack-based
replacement algorithms can be implemented without the drawbacks
of the traditional architectures. The stack is modular and hence, a set
of stack rows can be cascaded depending on the number of blocks in
each cache set. Our circuit can be implemented in conjunction with
the cache controller and static/dynamic memories to form a cache
system. Experimental results exhibit that our proposed circuit
provides an average value of 26% improvement in storage bits and its
maximum operating frequency is increased by a factor of two
Abstract: Studies on the distribution of traffic demands have
been proceeding by providing traffic information for reducing
greenhouse gases and reinforcing the road's competitiveness in the
transport section, however, since it is preferentially required the
extensive studies on the driver's behavior changing routes and its
influence factors, this study has been developed a discriminant model
for changing routes considering driving conditions including traffic
conditions of roads and driver's preferences for information media. It
is divided into three groups depending on driving conditions in group
classification with the CART analysis, which is statistically
meaningful. And the extent that driving conditions and preferred
media affect a route change is examined through a discriminant
analysis, and it is developed a discriminant model equation to predict a
route change. As a result of building the discriminant model equation,
it is shown that driving conditions affect a route change much more,
the entire discriminant hit ratio is derived as 64.2%, and this
discriminant equation shows high discriminant ability more than a
certain degree.