Abstract: An effective approach for realizing the binary tree structure, representing a combinational logic functionality with enhanced throughput, is discussed in this paper. The optimization in maximum operating frequency was achieved through delay minimization, which in turn was possible by means of reducing the depth of the binary network. The proposed synthesis methodology has been validated by experimentation with FPGA as the target technology. Though our proposal is technology independent, yet the heuristic enables better optimization in throughput even after technology mapping for such Boolean functionality; whose reduced CNF form is associated with a lesser literal cost than its reduced DNF form at the Boolean equation level. For cases otherwise, our method converges to similar results as that of [12]. The practical results obtained for a variety of case studies demonstrate an improvement in the maximum throughput rate for Spartan IIE (XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic families by 10.49% and 13.68% respectively. With respect to the LUTs and IOBUFs required for physical implementation of the requisite non-regenerative logic functionality, the proposed method enabled savings to the tune of 44.35% and 44.67% respectively, over the existing efficient method available in literature [12].
Abstract: This paper is taken into consideration the problem of cryptanalysis of stream ciphers. There is some attempts need to improve the existing attacks on stream cipher and to make an attempt to distinguish the portions of cipher text obtained by the encryption of plain text in which some parts of the text are random and the rest are non-random. This paper presents a tutorial introduction to symmetric cryptography. The basic information theoretic and computational properties of classic and modern cryptographic systems are presented, followed by an examination of the application of cryptography to the security of VoIP system in computer networks using LFSR algorithm. The implementation program will be developed Java 2. LFSR algorithm is appropriate for the encryption and decryption of online streaming data, e.g. VoIP (voice chatting over IP). This paper is implemented the encryption module of speech signals to cipher text and decryption module of cipher text to speech signals.
Abstract: One major difficulty that faces developers of
concurrent and distributed software is analysis for concurrency based
faults like deadlocks. Petri nets are used extensively in the
verification of correctness of concurrent programs. ECATNets are a
category of algebraic Petri nets based on a sound combination of
algebraic abstract types and high-level Petri nets. ECATNets have
'sound' and 'complete' semantics because of their integration in
rewriting logic and its programming language Maude. Rewriting
logic is considered as one of very powerful logics in terms of
description, verification and programming of concurrent systems We
proposed previously a method for translating Ada-95 tasking
programs to ECATNets formalism (Ada-ECATNet) and we showed
that ECATNets formalism provides a more compact translation for
Ada programs compared to the other approaches based on simple
Petri nets or Colored Petri nets. We showed also previously how the
ECATNet formalism offers to Ada many validation and verification
tools like simulation, Model Checking, accessibility analysis and
static analysis. In this paper, we describe the implementation of our
translation of the Ada programs into ECATNets.
Abstract: In order to survive in a rapidly changing business environment, Malaysian business firms must improve their own business practices and procedures. This paper describes the impact of Critical Success Factors (CSFs) during the Enterprise Resource Planning (ERP) system implementations using the responses from 151 organizations that completed or are in the process of completing an ERP implementation and identifying the key benefits of ERP implementation in the firm. The importance of these factors was investigated within Malaysian companies using questionnaire survey method. Our results provide advice to management on how best to utilize their limited resources to choose those CSFs that are most likely to have an impact upon the implementation of the ERP system.
Abstract: Conventional industrial monitoring systems are
tedious, inefficient and the at times integrity of the data is
unreliable. The objective of this system is to monitor industrial
processes specifically the fluid level which will measure the
instantaneous fluid level parameter and respond by text
messaging the exact value of the parameter to the user when
being enquired by a privileged access user. The development of
the embedded program code and the circuit for fluid level
measuring are discussed as well. Suggestions for future
implementations and efficient remote monitoring works are
included.
Abstract: In this paper, the implementation of low power,
high throughput convolutional filters for the one dimensional
Discrete Wavelet Transform and its inverse are presented. The
analysis filters have already been used for the implementation of a
high performance DWT encoder [15] with minimum memory
requirements for the JPEG 2000 standard. This paper presents the
design techniques and the implementation of the convolutional filters
included in the JPEG2000 standard for the forward and inverse DWT
for achieving low-power operation, high performance and reduced
memory accesses. Moreover, they have the ability of performing
progressive computations so as to minimize the buffering between
the decomposition and reconstruction phases. The experimental
results illustrate the filters- low power high throughput characteristics
as well as their memory efficient operation.
Abstract: The main objective of this study was to demonstrate that differentiation of infected and vaccinated animals (DIVA) strategy using different ELISA tests is possible when a subunit vaccine (Haemagglutinin protein) is used to prevent Avian influenza. Special emphasis was placed on the differentiation in the serological response to different components of the AIV (Nucleoprotein, Neuraminidase, Haemagglutinin, Nucleocapsid) between chickens that were vaccinated with a whole virus kill vaccine and recombinant vaccine. Furthermore, the potential use of this DIVA strategy using ELISA assays to detect Neuraminidase 1 (N1) was analyzed as strategy in countries where the field virus is H5N1 and the vaccine used is formulated with H5N2. Detection of AIV-s antibodies to any component in serum was negative for all animals on the study days 0-13. At study day 14 the titers of antibodies against Nucleoprotein (NP) and Nucleocapsid (NC) rose in the experimental groups vaccinated with Volvac® AI KV and were negatives during all the trial in the experimental groups vaccinated with a subunit H5; significant statistically differences were observed between these groups (p < 0.05). The seroconversion either Haemagglutinin or Neuraminidase was evident after 21 days post-vaccination in the experimental groups vaccinated with the respective viral fraction. Regarding the main aim of this study and according with the results that were obtained, use a combination of different ELISA test as a DIVA strategy is feasible when the vaccination is carry out with a subunit H5 vaccine. Also is possible to use the ELISA kit to detect Neuraminidase (either N1 or N2) as a DIVA concept in countries where H5N1 is present and the vaccination programs are done with H5N2 vaccine.
Abstract: An implementation of a design for a game based
virtual learning environment is described. The game is developed for a course in analogue electronics, and the topic is the design of a
power supply. This task can be solved in a number of different ways, with certain constraints, giving the students a certain amount of
freedom, although the game is designed not to facilitate trial-and error approach. The use of storytelling and a virtual gaming environment provides the student with the learning material in a
MMORPG environment. The game is tested on a group of second
year electrical engineering students with good results.
Abstract: Enterprise Wide Information Systems (EWIS)
implementation involves the entire business and will require changes
throughout the firm. Because of the scope, complexity and
continuous nature of ERP, the project-based approach to managing
the implementation process resulted in failure rates of between 60%
and 80%. In recent years ERP systems have received much attention.
The organizational relevance and risk of ERP projects make it
important for organizations to focus on ways to make ERP
implementation successful. Once these systems are in place,
however, their performance depends on the identified macro
variables viz. 'Business Process', 'Decision Making' and 'Individual
/ Group working'. The questionnaire was designed and administered.
The responses from 92 organizations were compiled. The
relationship of these variables with EWIS performance is analyzed
using inferential statistical measurements. The study helps to
understand the performance of model presented. The study suggested
in keeping away from the calamities and thereby giving the
necessary competitive edge. Whenever some discrepancy is
identified during the process of performance appraisal care has to be
taken to draft necessary preventive measures. If all these measures
are taken care off then the EWIS performance will definitely deliver
the results.
Abstract: This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: Block replacement algorithms to increase hit ratio
have been extensively used in cache memory management. Among
basic replacement schemes, LRU and FIFO have been shown to be
effective replacement algorithms in terms of hit rates. In this paper,
we introduce a flexible stack-based circuit which can be employed in
hardware implementation of both LRU and FIFO policies. We
propose a simple and efficient architecture such that stack-based
replacement algorithms can be implemented without the drawbacks
of the traditional architectures. The stack is modular and hence, a set
of stack rows can be cascaded depending on the number of blocks in
each cache set. Our circuit can be implemented in conjunction with
the cache controller and static/dynamic memories to form a cache
system. Experimental results exhibit that our proposed circuit
provides an average value of 26% improvement in storage bits and its
maximum operating frequency is increased by a factor of two
Abstract: This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).
Abstract: An implementation of current-mode multiphase sinusoidal oscillators is presented. Using CFTA-based lossy integrators, odd and odd/even phase systems can be realized with following advantages. The condition of oscillation and frequency of oscillation can be orthogonally tuned. The high output impedances facilitate easy driving an external load without additional current buffers. The proposed MSOs provide odd or even phase signals that are equally spaced in phase and equal amplitude. The circuit requires one CFTA, one resistor and one grounded capacitor per phase without additional current amplifier. The results of PSPICE simulations using CMOS CFTA are included to verify theory.
Abstract: This paper discusses the development of a qualitative
simulator (abbreviated QRiOM) for predicting the behaviour of
organic chemical reactions. The simulation technique is based on the
qualitative process theory (QPT) ontology. The modelling constructs
of QPT embody notions of causality which can be used to explain the
behaviour of a chemical system. The major theme of this work is
that, in a qualitative simulation environment, students are able to
articulate his/her knowledge through the inspection of explanations
generated by software. The implementation languages are Java and
Prolog. The software produces explanation in various forms that
stresses on the causal theories in the chemical system which can be
effectively used to support learning.
Abstract: For complete support of Quality of Service, it is better that environment itself predicts resource requirements of a job by using special methods in the Grid computing. The exact and correct prediction causes exact matching of required resources with available resources. After the execution of each job, the used resources will be saved in the active database named "History". At first some of the attributes will be exploit from the main job and according to a defined similarity algorithm the most similar executed job will be exploited from "History" using statistic terms such as linear regression or average, resource requirements will be predicted. The new idea in this research is based on active database and centralized history maintenance. Implementation and testing of the proposed architecture results in accuracy percentage of 96.68% to predict CPU usage of jobs and 91.29% of memory usage and 89.80% of the band width usage.
Abstract: In this paper we present an enhanced noise reduction method for robust speech recognition using Adaptive Gain Equalizer with Non linear Spectral Subtraction. In Adaptive Gain Equalizer method (AGE), the input signal is divided into a number of subbands that are individually weighed in time domain, in accordance to the short time Signal-to-Noise Ratio (SNR) in each subband estimation at every time instant. Instead of focusing on suppression the noise on speech enhancement is focused. When analysis was done under various noise conditions for speech recognition, it was found that Adaptive Gain Equalizer method algorithm has an obvious failing point for a SNR of -5 dB, with inadequate levels of noise suppression for SNR less than this point. This work proposes the implementation of AGE when coupled with Non linear Spectral Subtraction (AGE-NSS) for robust speech recognition. The experimental result shows that out AGE-NSS performs the AGE when SNR drops below -5db level.
Abstract: Recently, there have been considerable efforts towards the convergence between P2P and Grid computing in order to reach a solution that takes the best of both worlds by exploiting the advantages that each offers. Augmenting the peer-to-peer model to the services of the Grid promises to eliminate bottlenecks and ensure greater scalability, availability, and fault-tolerance. The Grid Information Service (GIS) directly influences quality of service for grid platforms. Most of the proposed solutions for decentralizing the GIS are based on completely flat overlays. The main contributions for this paper are: the investigation of a novel resource discovery framework for Grid implementations based on a hierarchy of structured peer-to-peer overlay networks, and introducing a discovery algorithm utilizing the proposed framework. Validation of the framework-s performance is done via simulation. Experimental results show that the proposed organization has the advantage of being scalable while providing fault-isolation, effective bandwidth utilization, and hierarchical access control. In addition, it will lead to a reliable, guaranteed sub-linear search which returns results within a bounded interval of time and with a smaller amount of generated traffic within each domain.
Abstract: A generalised relational data model is formalised for
the representation of data with nested structure of arbitrary depth. A
recursive algebra for the proposed model is presented. All the
operations are formally defined. The proposed model is proved to be
a superset of the conventional relational model (CRM). The
functionality and validity of the model is shown by a prototype
implementation that has been undertaken in the functional
programming language Miranda.
Abstract: In MPEG and H.26x standards, to eliminate the
temporal redundancy we use motion estimation. Given that the
motion estimation stage is very complex in terms of computational
effort, a hardware implementation on a re-configurable circuit is
crucial for the requirements of different real time multimedia
applications. In this paper, we present hardware architecture for
motion estimation based on "Full Search Block Matching" (FSBM)
algorithm. This architecture presents minimum latency, maximum
throughput, full utilization of hardware resources such as embedded
memory blocks, and combining both pipelining and parallel
processing techniques. Our design is described in VHDL language,
verified by simulation and implemented in a Stratix II
EP2S130F1020C4 FPGA circuit. The experiment result show that the
optimum operating clock frequency of the proposed design is 89MHz
which achieves 160M pixels/sec.