Abstract: Polylactic acid-g-polyvinyl acetate (PLLA-g-PVAc)
was used as a compatibilizer for 50/50 starch/PLLA blend. PLLA-g-
PVAc with different mol% of PVAc contents were prepared by
grafting PVAc onto PLLA backbone via free radical polymerization
in solution process. Various conditions such as type and the amount
of initiator, monomer concentration, polymerization time and
temperature were studied. Results showed that the highest mol% of
PVAc grafting (16 mol%) was achieved by conducting graft
copolymerization in toluene at 110°C for 10 h using DCP as an
initiator. Chemical structure of the PVAc grafted PLLA was
confirmed by 1H NMR. Blending of modified starch and PLLA in the
presence compatibilizer with different amounts and mol% PVAc was
acquired using internal mixer at 160°C for 15 min. Effects of PVAc
content and the amount of compatibilizer on mechanical properties of
polymer blend were studied. Results revealed that tensile strength and
tensile modulus of polymer blend with higher PVAc grafting content
compatibilizer showed better properties than that of lower PVAc
grafting content compatibilizer. The amount of compatibilizer was
found optimized in the range of 0.5-1.0 Wt% depending on the mol%
PVAc.
Abstract: Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.
Abstract: The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.
Abstract: In this paper the reference current for Voltage Source
Converter (VSC) of the Shunt Active Power Filter (SAPF) is
generated using Synchronous Reference Frame method,
incorporating the PI controller with anti-windup scheme. The
proposed method improves the harmonic filtering by compensating
the winding up phenomenon caused by the integral term of the PI
controller.
Using Reference Frame Transformation, the current is transformed
from om a - b - c stationery frame to rotating 0 - d - q frame. Using
the PI controller, the current in the 0 - d - q frame is controlled to
get the desired reference signal. A controller with integral action
combined with an actuator that becomes saturated can give some
undesirable effects. If the control error is so large that the integrator
saturates the actuator, the feedback path becomes ineffective because
the actuator will remain saturated even if the process output changes.
The integrator being an unstable system may then integrate to a very
large value, the phenomenon known as integrator windup.
Implementing the integrator anti-windup circuit turns off the
integrator action when the actuator saturates, hence improving the
performance of the SAPF and dynamically compensating harmonics
in the power network. In this paper the system performance is
examined with Shunt Active Power Filter simulation model.
Abstract: Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.
Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: This article deals to describe the simulation
investigation of the digital phase locked loop implemented in
software (SDPLL). SDPLL has been developed for speed drives of an
induction motor in scalar strategy. A drive was implemented and
simulation results are presented to verify the robustness against motor
parameter variation and regulation speed.
Abstract: An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.