Abstract: The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.
Abstract: Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.
Abstract: An approach to develop the FPGA of a flexible key
RSA encryption engine that can be used as a standard device in the
secured communication system is presented. The VHDL modeling of
this RSA encryption engine has the unique characteristics of
supporting multiple key sizes, thus can easily be fit into the systems
that require different levels of security. A simple nested loop addition
and subtraction have been used in order to implement the RSA
operation. This has made the processing time faster and used
comparatively smaller amount of space in the FPGA. The hardware
design is targeted on Altera STRATIX II device and determined that
the flexible key RSA encryption engine can be best suited in the
device named EP2S30F484C3. The RSA encryption implementation
has made use of 13,779 units of logic elements and achieved a clock
frequency of 17.77MHz. It has been verified that this RSA
encryption engine can perform 32-bit, 256-bit and 1024-bit
encryption operation in less than 41.585us, 531.515us and 790.61us
respectively.
Abstract: This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.
Abstract: In this paper, we propose the low-MAC FEC controller for practical implementation of JPEG2000 image transmission using IEEE 802.15.4. The proposed low-MAC FEC controller has very small HW size and spends little computation to estimate channel state. Because of this advantage, it is acceptable to apply IEEE 802.15.4 which has to operate more than 1 year with battery. For the image transmission, we integrate the low-MAC FEC controller and RCPC coder in sensor node of LR-WPAN. The modified sensor node has increase of 3% hardware size than conventional zigbee sensor node.
Abstract: Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.
Abstract: Data security in u-Health system can be an important
issue because wireless network is vulnerable to hacking. However, it is
not easy to implement a proper security algorithm in an embedded
u-health monitoring because of hardware constraints such as low
performance, power consumption and limited memory size and etc. To
secure data that contain personal and biosignal information, we
implemented several security algorithms such as Blowfish, data
encryption standard (DES), advanced encryption standard (AES) and
Rivest Cipher 4 (RC4) for our u-Health monitoring system and the
results were successful. Under the same experimental conditions, we
compared these algorithms. RC4 had the fastest execution time.
Memory usage was the most efficient for DES. However, considering
performance and safety capability, however, we concluded that AES
was the most appropriate algorithm for a personal u-Health monitoring
system.
Abstract: This paper describes the development, modeling, and
testing of skyhook and MiniMax control strategies of semi-active
suspension. The control performances are investigated using
Matlab/Simulink [1], with a two-degree-of-freedom quarter car semiactive
suspension system model. The comparison and evaluation of
control result are made using software-in-the-loop simulation (SILS)
method. This paper also outlines the development of a hardware-inthe-
loop simulation (HILS) system. The simulation results show that
skyhook strategy can significantly reduce the resonant peak of body
and provide improvement in vehicle ride comfort. Otherwise,
MiniMax strategy can be employed to effectively improve drive
safety of vehicle by influencing wheel load. The two strategies can
be switched to control semi-active suspension system to fulfill
different requirement of vehicle in different stages.
Abstract: This paper analyzed the perception of e-commerce
application services by construction material traders in Malaysia.
Five attributes were tested: usability, reputation, trust, privacy and
familiarity. Study methodology consists of survey questionnaire and
statistical analysis that includes reliability analysis, factor analysis,
ANOVA and regression analysis. The respondents were construction
material traders, including hardware stores in Klang Valley, Kuala
Lumpur.
Findings support that usability and familiarity with e-commerce
services in Malaysia have insignificant influence on the acceptance of
e-commerce application. However, reputation, trust and privacy
attributes have significant influence on the choice of e-commerce
acceptance by construction material traders. E-commerce
applications studied included customer database, e-selling, emarketing,
e-payment, e-buying and online advertising. Assumptions
are made that traders have basic knowledge and exposure to ICT
services. i.e. internet service and computers. Study concludes that
reputation, privacy and trust are the three website attributes that
influence the acceptance of e-commerce by construction material
traders.
Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
Abstract: In this paper the FPGA implementations for four
stream ciphers are presented. The two stream ciphers, MUGI and
SNOW 2.0 are recently adopted by the International Organization for
Standardization ISO/IEC 18033-4:2005 standard. The other two
stream ciphers, MICKEY 128 and TRIVIUM have been submitted
and are under consideration for the eSTREAM, the ECRYPT
(European Network of Excellence for Cryptology) Stream Cipher
project. All ciphers were coded using VHDL language. For the
hardware implementation, an FPGA device was used. The proposed
implementations achieve throughputs range from 166 Mbps for
MICKEY 128 to 6080 Mbps for MUGI.
Abstract: Signal processing applications which are iterative in
nature are best represented by data flow graphs (DFG). In these
applications, the maximum sampling frequency is dependent on the
topology of the DFG, the cyclic dependencies in particular. The
determination of the iteration bound, which is the reciprocal of the
maximum sampling frequency, is critical in the process of hardware
implementation of signal processing applications. In this paper, a
novel technique to compute the iteration bound is proposed. This
technique is different from all previously proposed techniques, in the
sense that it is based on the natural flow of tokens into the DFG
rather than the topology of the graph. The proposed algorithm has
lower run-time complexity than all known algorithms. The
performance of the proposed algorithm is illustrated through
analytical analysis of the time complexity, as well as through
simulation of some benchmark problems.
Abstract: In this paper, we propose improved versions of DVHop
algorithm as QDV-Hop algorithm and UDV-Hop algorithm for
better localization without the need for additional range measurement
hardware. The proposed algorithm focuses on third step of DV-Hop,
first error terms from estimated distances between unknown node and
anchor nodes is separated and then minimized. In the QDV-Hop
algorithm, quadratic programming is used to minimize the error to
obtain better localization. However, quadratic programming requires
a special optimization tool box that increases computational
complexity. On the other hand, UDV-Hop algorithm achieves
localization accuracy similar to that of QDV-Hop by solving
unconstrained optimization problem that results in solving a system
of linear equations without much increase in computational
complexity. Simulation results show that the performance of our
proposed schemes (QDV-Hop and UDV-Hop) is superior to DV-Hop
and DV-Hop based algorithms in all considered scenarios.
Abstract: Performance of vehicle depends on driving patterns
and vehicle drive train configuration. Driving patterns depends on
traffic condition, road condition and driver behavior. HEV design is
carried out under certain constrain like vehicle operating range,
acceleration, decelerations, maximum speed and road grades which
are directly related to the driving patterns. Therefore the detailed
study on HEV performance over a different drive cycle is required
for selection and sizing of HEV components. A simple hardware is
design to measured velocity v/s time profile of the vehicle by
operating vehicle on Indian roads under real traffic conditions. To
size the HEV components, a detailed dynamic model of the vehicle is
developed considering the effect of inertia of rotating components
like wheels, drive chain, engine and electric motor. Using vehicle
model and different Indian drive cycles data, total tractive power
demanded by vehicle and power supplied by individual components
has been calculated.Using above information selection and estimation
of component sizing for HEV is carried out so that HEV performs
efficiently under hostile driving condition. Complete analysis is
carried out in LABVIEW.
Abstract: Recently, much research has been conducted for
security for wireless sensor networks and ubiquitous computing.
Security issues such as authentication and data integrity are major
requirements to construct sensor network systems. Advanced
Encryption Standard (AES) is considered as one of candidate
algorithms for data encryption in wireless sensor networks. In this
paper, we will present the hardware architecture to implement low
power AES crypto module. Our low power AES crypto module has
optimized architecture of data encryption unit and key schedule unit
which could be applicable to wireless sensor networks. We also details
low power design methods used to design our low power AES crypto
module.
Abstract: Software-as-a-Service (SaaS) is a form of cloud
computing that relieves the user of the burden of hardware and
software installation and management. SaaS can be used at the course
level to enhance curricula and student experience. When cloud
computing and SaaS are included in educational literature, the focus
is typically on implementing administrative functions. Yet, SaaS can
make more immediate and substantial contributions to the technical
course content in educational offerings. This paper explores cloud
computing and SaaS, provides examples, reports on experiences
using SaaS to offer specialized software in courses, and analyzes the
advantages and disadvantages of using SaaS at the course level. The
paper contributes to the literature in higher education by analyzing
the major technical concepts, potential, and constraints for using
SaaS to deliver specialized software at the course level. Further it
may enable more educators and students to benefit from this
emerging technology.
Abstract: Data mining, which is the exploration of
knowledge from the large set of data, generated as a result of
the various data processing activities. Frequent Pattern Mining
is a very important task in data mining. The previous
approaches applied to generate frequent set generally adopt
candidate generation and pruning techniques for the
satisfaction of the desired objective. This paper shows how
the different approaches achieve the objective of frequent
mining along with the complexities required to perform the
job. This paper will also look for hardware approach of cache
coherence to improve efficiency of the above process. The
process of data mining is helpful in generation of support
systems that can help in Management, Bioinformatics,
Biotechnology, Medical Science, Statistics, Mathematics,
Banking, Networking and other Computer related
applications. This paper proposes the use of both upward and
downward closure property for the extraction of frequent item
sets which reduces the total number of scans required for the
generation of Candidate Sets.
Abstract: A novel low-cost flight simulator with the development
goals cost effectiveness and high performance has been realized for
meeting the huge pilot training needs of airlines. The simulator
consists of an aircraft dynamics model, a sophisticated designed
low-profile electrical driven motion system with a subsided cabin, a
mixed reality based semi-virtual cockpit system, a control loading
system and some other subsystems. It shows its advantages over
traditional flight simulator by its features achieved with open
architecture, software solutions and low-cost hardware.
Abstract: This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.