Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.