Abstract: The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.
Abstract: In the Solid-State-Drive (SSD) performance, whether
the data has been well parallelized is an important factor. SSD
parallelization is affected by allocation scheme and it is directly
connected to SSD performance. There are dynamic allocation and
static allocation in representative allocation schemes. Dynamic
allocation is more adaptive in exploiting write operation parallelism,
while static allocation is better in read operation parallelism.
Therefore, it is hard to select the appropriate allocation scheme when
the workload is mixed read and write operations. We simulated
conditions on a few mixed data patterns and analyzed the results to
help the right choice for better performance. As the results, if data
arrival interval is long enough prior operations to be finished and
continuous read intensive data environment static allocation is more
suitable. Dynamic allocation performs the best on write performance
and random data patterns.
Abstract: To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
Abstract: The energy consumption and delay in read/write
operation of conventional SRAM is investigated analytically as well
as by simulation. Explicit analytical expressions for the energy
consumption and delay in read and write operation as a function of
device parameters and supply voltage are derived. The expressions are
useful in predicting the effect of parameter changes on the energy
consumption and speed as well as in optimizing the design of
conventional SRAM. HSPICE simulation in standard 0.25μm CMOS
technology confirms precision of analytical expressions derived from
this paper.
Abstract: This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.
Abstract: This paper proposes a low power SRAM based on
five transistor SRAM cell. Proposed SRAM uses novel word-line
decoding such that, during read/write operation, only selected cell
connected to bit-line whereas, in conventional SRAM (CV-SRAM),
all cells in selected row connected to their bit-lines, which in turn
develops differential voltages across all bit-lines, and this makes
energy consumption on unselected bit-lines. In proposed SRAM
memory array divided into two halves and this causes data-line
capacitance to reduce. Also proposed SRAM uses one bit-line and
thus has lower bit-line leakage compared to CV-SRAM.
Furthermore, the proposed SRAM incurs no area overhead, and has
comparable read/write performance versus the CV-SRAM.
Simulation results in standard 0.25μm CMOS technology shows in
worst case proposed SRAM has 80% smaller dynamic energy
consumption in each cycle compared to CV-SRAM. Besides, energy
consumption in each cycle of proposed SRAM and CV-SRAM
investigated analytically, the results of which are in good agreement
with the simulation results.