Abstract: In this paper, a framework for the simplification and
standardization of metaheuristic related parameter-tuning by applying
a four phase methodology, utilizing Design of Experiments and
Artificial Neural Networks, is presented. Metaheuristics are multipurpose
problem solvers that are utilized on computational optimization
problems for which no efficient problem specific algorithm
exist. Their successful application to concrete problems requires the
finding of a good initial parameter setting, which is a tedious and
time consuming task. Recent research reveals the lack of approach
when it comes to this so called parameter-tuning process. In the
majority of publications, researchers do have a weak motivation for
their respective choices, if any. Because initial parameter settings
have a significant impact on the solutions quality, this course of
action could lead to suboptimal experimental results, and thereby
a fraudulent basis for the drawing of conclusions.
Abstract: The purpose of this work is fast design optimization of
the seal chamber. The study includes the mass transfer between lower
and upper chamber on seal chamber for hot water application pumps.
The use of Fluent 12.1 commercial code made it possible to capture
complex flow with heat-mass transfer, radiation, Tailor instability,
and buoyancy effect. Realizable k-epsilon model was used for
turbulence modeling. Radiation heat losses were taken into account.
The temperature distribution at seal region is predicted with respect
to heat addition.
Results show the possibilities of the model simplifications by
excluding the water domain in low chamber from calculations. CFD
simulations permit to improve seal chamber design to meet target
water temperature around the seal. This study can be used for the
analysis of different seal chamber configurations.
Abstract: Air bending is one of the important metal forming
processes, because of its simplicity and large field application.
Accuracy of analytical and empirical models reported for the analysis
of bending processes is governed by simplifying assumption and do
not consider the effect of dynamic parameters. Number of researches
is reported on the finite element analysis (FEA) of V-bending, Ubending,
and air V-bending processes. FEA of bending is found to be
very sensitive to many physical and numerical parameters. FE
models must be computationally efficient for practical use. Reported
work shows the 3D FEA of air bending process using Hyperform LSDYNA
and its comparison with, published 3D FEA results of air
bending in Ansys LS-DYNA and experimental results. Observing the
planer symmetry and based on the assumption of plane strain
condition, air bending problem was modeled in 2D with symmetric
boundary condition in width. Stress-strain results of 2D FEA were
compared with 3D FEA results and experiments. Simplification of
air bending problem from 3D to 2D resulted into tremendous
reduction in the solution time with only marginal effect on stressstrain
results. FE model simplification by studying the problem
symmetry is more efficient and practical approach for solution of
more complex large dimensions slow forming processes.
Abstract: Several optimization algorithms specifically applied to
the problem of Operation Planning of Hydrothermal Power Systems
have been developed and are used. Although providing solutions to
various problems encountered, these algorithms have some
weaknesses, difficulties in convergence, simplification of the original
formulation of the problem, or owing to the complexity of the
objective function. Thus, this paper presents the development of a
computational tool for solving optimization problem identified and to
provide the User an easy handling. Adopted as intelligent
optimization technique, Genetic Algorithms and programming
language Java. First made the modeling of the chromosomes, then
implemented the function assessment of the problem and the
operators involved, and finally the drafting of the graphical interfaces
for access to the User. The program has managed to relate a coherent
performance in problem resolution without the need for
simplification of the calculations together with the ease of
manipulating the parameters of simulation and visualization of output
results.
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.