Abstract: Minimally invasive surgery (MIS) is now being widely used as a preferred choice for various types of operations. The need to detect various tactile properties, justifies the key role of tactile sensing that is currently missing in MIS. In this regard, Laparoscopy is one of the methods of minimally invasive surgery that can be used in kidney stone removal surgeries. At this moment, determination of the exact location of stone during laparoscopy is one of the limitations of this method that no scientific solution has been found for so far. Artificial tactile sensing is a new method for obtaining the characteristics of a hard object embedded in a soft tissue. Artificial palpation is an important application of artificial tactile sensing that can be used in different types of surgeries. In this study, a new method for determining the exact location of stone during laparoscopy is presented. In the present study, the effects of stone existence on the surface of kidney were investigated using conceptual 3D model of kidney containing a simulated stone. Having imitated palpation and modeled it conceptually, indications of stone existence that appear on the surface of kidney were determined. A number of different cases were created and solved by the software and using stress distribution contours and stress graphs, it is illustrated that the created stress patterns on the surface of kidney show not only the existence of stone inside, but also its exact location. So three-dimensional analysis leads to a novel method of predicting the exact location of stone and can be directly applied to the incorporation of tactile sensing in artificial palpation, helping surgeons in non-invasive procedures.
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.
Abstract: In this paper by measuring the cutting forces the effect
of the tool shape and qualifications (sharp and worn cutting tools of
both vee and knife edge profile) and cutting conditions (depth of cut
and cutting speed) in the turning operation on the tool deflection and
cutting force is investigated. The workpiece material was mild steel
and the cutting tool was made of high speed steel. Cutting forces
were measured by a dynamometer (type P.E.I. serial No 154). The
dynamometer essentially consisted of a cantilever structure which
held the cutting tool. Deflection of the cantilever was measured by an
L.V.D.T (Mercer 122) deflection indicator. No cutting fluid was used
during the turning operations. A modern CNC lathe machine (Okuma
LH35-N) was used for the tests. It was noted that worn vee profile
tools tended to produce a greater increase in the vertical force
component than the axial component, whereas knife tools tended to
show a more pronounced increase in the axial component.