Abstract: Conventional approaches in the implementation of logic programming applications on embedded systems are solely of software nature. As a consequence, a compiler is needed that transforms the initial declarative logic program to its equivalent procedural one, to be programmed to the microprocessor. This approach increases the complexity of the final implementation and reduces the overall system's performance. On the contrary, presenting hardware implementations which are only capable of supporting logic programs prevents their use in applications where logic programs need to be intertwined with traditional procedural ones, for a specific application. We exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of those derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation is programmable, supports the execution of hybrid applications, increases the performance of logic derivations (experimental analysis yields an approximate 1000% increase in performance) and reduces the complexity of the final implemented code. The proposed hardware design is supported by a proposed extended C-language called C-AG.
Abstract: Tasks of an application program of an embedded system are managed by the scheduler of a real-time operating system
(RTOS). Most RTOSs adopt just fixed priority scheduling, which is not optimal in all cases. Some applications require earliest deadline
first (EDF) scheduling, which is an optimal scheduling algorithm.
In order to develop an efficient real-time embedded system, the
scheduling algorithm of the RTOS should be selectable. The paper presents a method to customize the scheduler using aspectoriented
programming. We define aspects to replace the fixed priority scheduling mechanism of an OSEK OS with an EDF scheduling
mechanism. By using the aspects, we can customize the scheduler
without modifying the original source code. We have applied the
aspects to an OSEK OS and get a customized operating system with
EDF scheduling. The evaluation results show that the overhead of
aspect-oriented programming is small enough.
Abstract: A separation-kernel-based operating system (OS) has been designed for use in secure embedded systems by applying formal methods to the design of the separation-kernel part. The separation kernel is a small OS kernel that provides an abstract distributed environment on a single CPU. The design of the separation kernel was verified using two formal methods, the B method and the Spin model checker. A newly designed semi-formal method, the extended state transition method, was also applied. An OS comprising the separation-kernel part and additional OS services on top of the separation kernel was prototyped on the Intel IA-32 architecture. Developing and testing of a prototype embedded application, a point-of-sale application, on the prototype OS demonstrated that the proposed architecture and the use of formal methods to design its kernel part are effective for achieving a secure embedded system having a high-assurance separation kernel.
Abstract: This paper presents preliminary results regarding system-level power awareness for FPGA implementations in wireless sensor networks. Re-configurability of field programmable gate arrays (FPGA) allows for significant flexibility in its applications to embedded systems. However, high power consumption in FPGA becomes a significant factor in design considerations. We present several ideas and their experimental verifications on how to optimize power consumption at high level of designing process while maintaining the same energy per operation (low-level methods can be used additionally). This paper demonstrates that it is possible to estimate feasible power consumption savings even at the high level of designing process. It is envisaged that our results can be also applied to other embedded systems applications, not limited to FPGA-based.
Abstract: Long number multiplications (n ≥ 128-bit) are a
primitive in most cryptosystems. They can be performed better by
using Karatsuba-Ofman technique. This algorithm is easy to
parallelize on workstation network and on distributed memory, and
it-s known as the practical method of choice. Multiplying long
numbers using Karatsuba-Ofman algorithm is fast but is highly
recursive. In this paper, we propose different designs of
implementing Karatsuba-Ofman multiplier. A mixture of sequential
and combinational system design techniques involving pipelining is
applied to our proposed designs. Multiplying large numbers can be
adapted flexibly to time, area and power criteria. Computationally
and occupation constrained in embedded systems such as: smart
cards, mobile phones..., multiplication of finite field elements can be
achieved more efficiently. The proposed designs are compared to
other existing techniques. Mathematical models (Area (n), Delay (n))
of our proposed designs are also elaborated and evaluated on
different FPGAs devices.
Abstract: The paper presents a set of guidelines for analysis of industrial embedded distributed systems and introduces a mathematical model derived from these guidelines. In this study, the author examines a set of modern communication technologies that are or possibly can be used to build communication links between the subsystems of a distributed embedded system. An investigation of these guidelines results in a algorithm for analysis of specific use cases of target technologies. A goal of the paper acts as an important base for ongoing research on comparison of communication technologies. The author describes the principles of the model and presents results of the test calculations. Practical implementation of target technologies and empirical experiment data are based on a practical experience during the design and test of specific distributed systems in Latvian market.
Abstract: Traditional development of wireless sensor network
mote is generally based on SoC1 platform. Such method of
development faces three main drawbacks: lack of flexibility in terms
of development due to low resource and rigid architecture of SoC;
low capability of evolution and portability versus performance if
specific micro-controller architecture features are used; and the rapid
obsolescence of micro-controller comparing to the long lifetime of
power plants or any industrial installations. To overcome these
drawbacks, we have explored a new approach of development of
wireless sensor network mote using a hybrid FPGA technology. The
application of such approach is illustrated through the
implementation of an innovative wireless sensor network protocol
called OCARI.
Abstract: An embedded system for SEU(single event upset) test
needs to be designed to prevent system failure by high-energy particles
during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for
SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which
manages the DUT and measures the occurrence of SEU. It needs to
have considerations for preventing system failure while managing the
DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different
cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.
Abstract: Model Predictive Control (MPC) is increasingly being
proposed for real time applications and embedded systems. However
comparing to PID controller, the implementation of the MPC in
miniaturized devices like Field Programmable Gate Arrays (FPGA)
and microcontrollers has historically been very small scale due to its
complexity in implementation and its computation time requirement.
At the same time, such embedded technologies have become an
enabler for future manufacturing enterprises as well as a transformer
of organizations and markets. Recently, advances in microelectronics
and software allow such technique to be implemented in embedded
systems. In this work, we take advantage of these recent advances
in this area in the deployment of one of the most studied and
applied control technique in the industrial engineering. In fact in
this paper, we propose an efficient framework for implementation
of Generalized Predictive Control (GPC) in the performed STM32
microcontroller. The STM32 keil starter kit based on a JTAG interface
and the STM32 board was used to implement the proposed GPC
firmware. Besides the GPC, the PID anti windup algorithm was
also implemented using Keil development tools designed for ARM
processor-based microcontroller devices and working with C/Cµ
langage. A performances comparison study was done between both
firmwares. This performances study show good execution speed and
low computational burden. These results encourage to develop simple
predictive algorithms to be programmed in industrial standard hardware.
The main features of the proposed framework are illustrated
through two examples and compared with the anti windup PID
controller.
Abstract: This paper presents a web based remote access
microcontroller laboratory. Because of accelerated development in
electronics and computer technologies, microcontroller-based devices
and appliances are found in all aspects of our daily life. Before the
implementation of remote access microcontroller laboratory an
experiment set is developed by teaching staff for training
microcontrollers. Requirement of technical teaching and industrial
applications are considered when experiment set is designed.
Students can make the experiments by connecting to the experiment
set which is connected to the computer that set as the web server. The
students can program the microcontroller, can control digital and
analog inputs and can observe experiment. Laboratory experiment
web page can be accessed via www.elab.aku.edu.tr address.
Abstract: The paper discusses complexity of component-based
development (CBD) of embedded systems. Although CBD has its
merits, it must be augmented with methods to control the complexities
that arise due to resource constraints, timeliness, and run-time deployment
of components in embedded system development. Software
component specification, system-level testing, and run-time reliability
measurement are some ways to control the complexity.
Abstract: Introducing Electromagnetic Interference and Electromagnetic Compatibility, or “The Art of Black Magic", for engineering students might be a terrifying experience both for students and tutors. Removing the obstacle of large, expensive facilities like a fully fitted EMC laboratory and hours of complex theory, this paper demonstrates a design of a laboratory setup for student exercises, giving students experience in the basics of EMC/EMI problems that may challenge the functionality and stability of embedded system designs. This is done using a simple laboratory installation and basic measurement equipment such as a medium cost digital storage oscilloscope, at the cost of not knowing the exact magnitude of the noise components, but rather if the noise is significant or not, as well as the source of the noise. A group of students have performed a trial exercise with good results and feedback.
Abstract: This paper studies the dependability of componentbased
applications, especially embedded ones, from the diagnosis
point of view. The principle of the diagnosis technique is to
implement inter-component tests in order to detect and locate the
faulty components without redundancy. The proposed approach for
diagnosing faulty components consists of two main aspects. The first
one concerns the execution of the inter-component tests which
requires integrating test functionality within a component. This is the
subject of this paper. The second one is the diagnosis process itself
which consists of the analysis of inter-component test results to
determine the fault-state of the whole system. Advantage of this
diagnosis method when compared to classical redundancy faulttolerant
techniques are application autonomy, cost-effectiveness and
better usage of system resources. Such advantage is very important
for many systems and especially for embedded ones.
Abstract: Real-time embedded systems should benefit from
component-based software engineering to handle complexity and
deal with dependability. In these systems, applications should not
only be logically correct but also behave within time windows.
However, in the current component based software engineering
approaches, a few of component models handles time properties in
a manner that allows efficient analysis and checking at the
architectural level. In this paper, we present a meta-model for
component-based software description that integrates timing
issues. To achieve a complete functional model of software
components, our meta-model focuses on four functional aspects:
interface, static behavior, dynamic behavior, and interaction
protocol. With each aspect we have explicitly associated a time
model. Such a time model can be used to check a component-s
design against certain properties and to compute the timing
properties of component assemblies.
Abstract: The more recent satellite projects/programs makes
extensive usage of real – time embedded systems. 16 bit processors
which meet the Mil-Std-1750 standard architecture have been used in
on-board systems. Most of the Space Applications have been written
in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are
needed in the area of spacecraft computing and therefore an effort is
desirable in the study and survey of 64 bit architectures for space
applications. This will also result in significant technology
development in terms of VLSI and software tools for ADA (as the
legacy code is in ADA).
There are several basic requirements for a special processor for
this purpose. They include Radiation Hardened (RadHard) devices,
very low power dissipation, compatibility with existing operational
systems, scalable architectures for higher computational needs,
reliability, higher memory and I/O bandwidth, predictability, realtime
operating system and manufacturability of such processors.
Further on, these may include selection of FPGA devices, selection
of EDA tool chains, design flow, partitioning of the design, pin
count, performance evaluation, timing analysis etc.
This project deals with a brief study of 32 and 64 bit processors
readily available in the market and designing/ fabricating a 64 bit
RISC processor named RISC MicroProcessor with added
functionalities of an extended double precision floating point unit
and a 32 bit signal processing unit acting as co-processors. In this
paper, we emphasize the ease and importance of using Open Core
(OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as
Icarus to develop FPGA based prototypes quickly. Commercial tools
such as Xilinx ISE for Synthesis are also used when appropriate.
Abstract: A novel low-cost impedance control structure is
proposed for monitoring the contact force between end-effector and
environment without installing an expensive force/torque sensor.
Theoretically, the end-effector contact force can be estimated from the
superposition of each joint control torque. There have a nonlinear
matrix mapping function between each joint motor control input and
end-effector actuating force/torques vector. This new force control
structure can be implemented based on this estimated mapping matrix.
First, the robot end-effector is manipulated to specified positions, then
the force controller is actuated based on the hall sensor current
feedback of each joint motor. The model-free fuzzy sliding mode
control (FSMC) strategy is employed to design the position and force
controllers, respectively. All the hardware circuits and software
control programs are designed on an Altera Nios II embedded
development kit to constitute an embedded system structure for a
retrofitted Mitsubishi 5 DOF robot. Experimental results show that PI
and FSMC force control algorithms can achieve reasonable contact
force monitoring objective based on this hardware control structure.
Abstract: Safer driver behavior promoting is the main goal of this paper. It is a fact that drivers behavior is relatively safer when being monitored. Thus, in this paper, we propose a monitoring system to report specific driving event as well as the potentially aggressive events for estimation of the driving performance. Our driving monitoring system is composed of two parts. The first part is the in-vehicle embedded system which is composed of a GPS receiver, a two-axis accelerometer, radar sensor, OBD interface, and GPRS modem. The design considerations that led to this architecture is described in this paper. The second part is a web server where an adaptive hierarchical fuzzy system is proposed to classify the driving performance based on the data that is sent by the in-vehicle embedded system and the data that is provided by the geographical information system (GIS). Our system is robust, inexpensive and small enough to fit inside a vehicle without distracting the driver.
Abstract: In today-s era of plasma and laser cutting, machines using oxy-acetylene flame are also meritorious due to their simplicity and cost effectiveness. The objective to devise a Computer controlled Oxy-Fuel profile cutting machine arose from the increasing demand for metal cutting with respect to edge quality, circularity and lesser formation of redeposit material. The System has an 8 bit micro controller based embedded system, which assures stipulated time response. A new window based Application software was devised which takes a standard CAD file .DXF as input and converts it into numerical data required for the controller. It uses VB6 as a front end whereas MS-ACCESS and AutoCAD as back end. The system is designed around AT89C51RD2, powerful 8 bit, ISP micro controller from Atmel and is optimized to achieve cost effectiveness and also maintains the required accuracy and reliability for complex shapes. The backbone of the system is a cleverly designed mechanical assembly along with the embedded system resulting in an accuracy of about 10 microns while maintaining perfect linearity in the cut. This results in substantial increase in productivity. The observed results also indicate reduced inter laminar spacing of pearlite with an increase in the hardness of the edge region.
Abstract: The research on two-wheeled inverted pendulum (TWIP) mobile robots or commonly known as balancing robots have gained momentum over the last decade in a number of robotic laboratories around the world. This paper describes the hardware design of such a robot. The objective of the design is to develop a TWIP mobile robot as well as MATLAB interfacing configuration to be used as flexible platform comprises of embedded unstable linear plant intended for research and teaching purposes. Issues such as selection of actuators and sensors, signal processing units, MATLAB Real Time Workshop coding, modeling and control scheme will be addressed and discussed. The system is then tested using a wellknown state feedback controller to verify its functionality.
Abstract: Embedded systems need to respect stringent real
time constraints. Various hardware components included in such
systems such as cache memories exhibit variability and therefore
affect execution time. Indeed, a cache memory access from an
embedded microprocessor might result in a cache hit where the
data is available or a cache miss and the data need to be fetched
with an additional delay from an external memory. It is therefore
highly desirable to predict future memory accesses during
execution in order to appropriately prefetch data without incurring
delays. In this paper, we evaluate the potential of several artificial
neural networks for the prediction of instruction memory
addresses. Neural network have the potential to tackle the nonlinear
behavior observed in memory accesses during program
execution and their demonstrated numerous hardware
implementation emphasize this choice over traditional forecasting
techniques for their inclusion in embedded systems. However,
embedded applications execute millions of instructions and
therefore millions of addresses to be predicted. This very
challenging problem of neural network based prediction of large
time series is approached in this paper by evaluating various neural
network architectures based on the recurrent neural network
paradigm with pre-processing based on the Self Organizing Map
(SOM) classification technique.