Abstract: This paper describes design of a digital feedback loop
for a low switching frequency dc-dc switching converters. Low
switching frequencies were selected in this design. A look up table
for the digital PID (proportional integrator differentiator)
compensator was implemented using Altera Stratix II with built-in
ADC (analog-to-digital converter) to achieve this hardware
realization. Design guidelines are given for the PID compensator,
high frequency DPWM (digital pulse width modulator) and moving
average filter.
Abstract: A new power regulator controller with multiple-access
PID compensator is proposed, which can achieve a minimum memory
requirement for fully table look-up. The proposed regulator controller
employs hysteresis comparators, an error process unit (EPU) for
voltage regulation, a multiple-access PID compensator and a lowpower-
consumption digital PWM (DPWM). Based on the multipleaccess
mechanism, the proposed controller can alleviate the penalty of
large amount of memory employed for fully table look-up based PID
compensator in the applications of power regulation. The proposed
controller has been validated with simulation results.