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International Journal of Electrical, Electronic and Communication Sciences

ISSN: 2517-9438

Total 24 content found

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A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique

Year: 2007 Volume: 1 Issue: 7 963 - 965 Pages

Abstract: This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.

Investigation of Interference Conditions in BFWA System Applying Adaptive TDD

Year: 2007 Volume: 1 Issue: 7 957 - 962 Pages

Abstract: In a BFWA (Broadband Fixed Wireless Access Network) the evolved SINR (Signal to Interference plus Noise Ratio) is relevant influenced by the applied duplex method. The TDD (Time Division Duplex), especially adaptive TDD method has some advantage contrary to FDD (Frequency Division Duplex), for example the spectrum efficiency and flexibility. However these methods are suffering several new interference situations that can-t occur in a FDD system. This leads to reduced SINR in the covered area what could cause some connection outages. Therefore, countermeasure techniques against interference are necessary to apply in TDD systems. Synchronization is one way to handling the interference. In this paper the TDD systems – applying different system synchronization degree - will be compared by the evolved SINR at different locations of the BFWA service area and the percentage of the covered area by the system.

Combining the Description Features of UMLRT and CSP+T Specifications Applied to a Complete Design of Real-Time Systems

Year: 2007 Volume: 1 Issue: 7 951 - 956 Pages

Abstract: UML is a collection of notations for capturing a software system specification. These notations have a specific syntax defined by the Object Management Group (OMG), but many of their constructs only present informal semantics. They are primarily graphical, with textual annotation. The inadequacies of standard UML as a vehicle for complete specification and implementation of real-time embedded systems has led to a variety of competing and complementary proposals. The Real-time UML profile (UML-RT), developed and standardized by OMG, defines a unified framework to express the time, scheduling and performance aspects of a system. We present in this paper a framework approach aimed at deriving a complete specification of a real-time system. Therefore, we combine two methods, a semiformal one, UML-RT, which allows the visual modeling of a realtime system and a formal one, CSP+T, which is a design language including the specification of real-time requirements. As to show the applicability of the approach, a correct design of a real-time system with hard real time constraints by applying a set of mapping rules is obtained.

Encoding and Compressing Data for Decreasing Number of Switches in Baseline Networks

Year: 2007 Volume: 1 Issue: 7 946 - 950 Pages

Abstract: This method decrease usage power (expenditure) in networks on chips (NOC). This method data coding for data transferring in order to reduces expenditure. This method uses data compression reduces the size. Expenditure calculation in NOC occurs inside of NOC based on grown models and transitive activities in entry ports. The goal of simulating is to weigh expenditure for encoding, decoding and compressing in Baseline networks and reduction of switches in this type of networks. KeywordsNetworks on chip, Compression, Encoding, Baseline networks, Banyan networks.