Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA

Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx and modelsim uses for showing results.

Authors:

• S. Heydarzadeh
• A. Kadivarian
• P. Torkzadeh

Keywords:

• Analog to digital converter
• Successive approximation
• Capacitor switching algorithm
• FPGA

References:

[1] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, "A 0.92mW10-bit
50-MS/s SAR ADC in 0.13 ╬╝m CMOS process," in IEEE Symp. VLSI
Circuits Dig., Jun. 2009, pp. 236-237.
[2] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and
J. Craninckx, "An 820 ╬╝W 9 b 40 MS/s noise-tolerant dynamic-SAR
ADC in 90 nm digital CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb.
2008, pp. 238-239.
[3] J.Gan,S.Yan,J. Abraham, "Design and Modeling of a 16-bit 1.5MSPS
Successive Approximation ADC with Non-binary Capacitor Array, "
GLSVLSI -03, April 28-29, 2003, Washington, DC, USA.
[4] EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design -
2009.
[5] Ch-Ch.Liu, S-J. Chang,G-Y. Huang, Y-Z Lin, "A 10-bit 50-MS/s SAR
ADC With a Monotonic Capacitor Switching Procedure, " IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL
2010.
[6] M. Yoshioka, et Al. "A 10b 50MS/s 820 ╬╝W SAR ADC withOn-Chip
Digital Calibration," IEEE ISSCC Dig. Tech. Papers,pp. 384-385, Feb.
2010.
[7] F. Kuttner, "A 1.2-V 10-b 20-Msample/s nonbinary successive
approximation ADC in 0.13-╬╝m CMOS," in IEEE ISSCC Dig. Tech.
Papers,Feb. 2002, pp. 176-177.
[8] T. Kugelstadt, "The Operation of the SAR-ADC Based on Charge
Redistribution", Texas Instruments Analog Applications Journal, Feb.
2000, pp. 10-12.
[9] Gilbert Promitzer, "12 Bit Low Power Fully Differential Switched
Capacitor Non-Calibrating Successive Approximation ADC with
1MS/s," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, July.
2001.