C-V Characterization and Analysis of Temperature and Channel Thickness Effects on Threshold Voltage of Ultra-thin SOI MOSFET by Self-Consistent Model
The threshold voltage and capacitance voltage characteristics of ultra-thin Silicon-on-Insulator MOSFET are greatly influenced by the thickness and doping concentration of the silicon film. In this work, the capacitance voltage characteristics and threshold voltage of the device have been analyzed with quantum mechanical effects using the Self-Consistent model. Reduction of channel thickness and adding doping impurities cause an increase in the threshold voltage. Moreover, the temperature effects cause a significant amount of threshold voltage shift. The temperature dependence of threshold voltage has also been observed with Self- Consistent approach which are well supported from experimental performance of practical devices.
[1] S. Kim, T. Shim, and J. Park, "Electrical behavior of ultra-thin body
silicon-on-insulator n-mosfets at a high operating temperaure," Journal
of Ceramic Processing Reseach, vol. 10, no. 4, pp. 507 -511, 2009.
[2] Y. Omura, A. Nakakubo, and H. Nakatsuji, "Quantum mechanical
effect in temperature dependence of threshold voltage of extremely
thin soi mosfets," Solid-State Electronics, vol. 48, no. 9, pp. 1661 -
1666, 2004, non Volatile Memories with discrete storage nodes. (Online).
Available: http://www.sciencedirect.com/science/article/B6TY5-
4CDHD5K-2/2/4ce9ebb7270ac96308d1ce7efda02d80
[3] H.-K. Lim and J. Fossum, "Threshold voltage of thin-film siliconon-
insulator (soi) mosfet-s," Electron Devices, IEEE Transactions on,
vol. 30, no. 10, pp. 1244 - 1251, oct 1983.
[4] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono,
Y. Takahashi, and K. Murase, "Ultimately thin double-gate soi mosfets,"
Electron Devices, IEEE Transactions on, vol. 50, no. 3, pp. 830 - 838,
march 2003.
[5] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor,
and C. Hu, "Ultra-thin body soi mosfet for deep-sub-tenth micron era," in
Electron Devices Meeting, 1999. IEDM Technical Digest. International,
1999, pp. 919 -921.
[6] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical
effects on the threshold voltage of ultrathin-soi nmosfets," Electron
Device Letters, IEEE, vol. 14, no. 12, pp. 569 -571, dec 1993.
[7] D. Flandre, A. Terao, P. Francis, B. Gentinne, and J.-P. Colinge,
"Demonstration of the potential of accumulation-mode mos transistors
on soi substrates for high-temperature operation (150-300 deg;c)," Electron
Device Letters, IEEE, vol. 14, no. 1, pp. 10 -12, jan 1993.
[8] G. Groeseneken, J.-P. Colinge, H. Maes, J. Alderman, and S. Holt,
"Temperature dependence of threshold voltage in thin-film soi mosfets,"
Electron Device Letters, IEEE, vol. 11, no. 8, pp. 329 -331, aug 1990.
[9] M. Shams, M. Alam, and Q. Khosru, "Effect of uniaxial strain on the
gate capacitance of double gate mosfets," in Electron Devices and Solid-
State Circuits, 2008. EDSSC 2008. IEEE International Conference on,
Dec 2008, pp. 1 -4.
[10] M. Shams, K. Habib, R. Mikail, Q. D. M. Khosru, A. Zainuddin,
and A. Haque, "An improved physically based compact c-v model for
mos devices with high-k gate dielectrics," in Electrical and Computer
Engineering, 2006. ICECE -06. International Conference on, 19-21
2006, pp. 518 -521.
[11] S. Ahmed, Ahsan-Ul-Alam, M. Alam, and Q. Khosru, "Gate leakage
current of a double gate n-mos on (111) silicon - a quantum mechanical
study," in Computer and Communication Engineering, 2008. ICCCE
2008. International Conference on, 13-15 2008, pp. 960 -963.
[12] B. Afzal, A. Zahabi, A. Amirabadi, Y. Koolivand, A. Afzali-
Kusha, and M. E. Nokali, "Analytical model for c-v characteristic
of fully depleted soi-mos capacitors," Solid-State Electronics,
vol. 49, no. 8, pp. 1262 - 1273, 2005. (Online). Available:
http://www.sciencedirect.com/science/article/B6TY5-4GSJXNG-
1/2/b2e3fd3db337369e3dac71c3cf389f3f
[13] F. Ikraiam, R. Beck, and A. Jakubowski, "Modeling of soi-mos capacitors
c-v behavior: partially- and fully-depleted cases," Electron Devices,
IEEE Transactions on, vol. 45, no. 5, pp. 1026 -1032, may 1998.
[14] S. C. Rustagi, Z. O. Mohsen, S. Chandra, and A. Chand,
"C-v characterization of mos capacitors in soi structures," Solid-
State Electronics, vol. 39, no. 6, pp. 841 - 849, 1996. (Online).
Available: http://www.sciencedirect.com/science/article/B6TY5-
3VTNT9C-19/2/f30b05629516edb8750425d53140d77e
[15] A. Haque and M. Kauser, "A comparison of wave-function penetration
effects on gate capacitance in deep submicron n- and p-mosfets,"
Electron Devices, IEEE Transactions on, vol. 49, no. 9, pp. 1580 -
1587, sep 2002.
[16] N. Weste, D. Harris, and A. Banarjee, CMOS VLSI Design : A Circuits
and Systems Perspective, 3rd ed. USA: Pearson Education Inc., 2008.
[17] L. Chang, K. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu,
"Direct-tunneling gate leakage current in double-gate and ultrathin body
mosfets," Electron Devices, IEEE Transactions on, vol. 49, no. 12, pp.
2288 - 2295, dec 2002.
[18] S. Sze and K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken,
NJ, USA: John Wiley & Sons, Inc., April 2006.
[19] R. F. Pierret, Advanced Semiconductor Fundamentals, 2nd ed., ser.
Modular Series on Solid State Devices, R. Pierret and G. Neudeck,
Eds. Upper Saddle River, NJ, USA: Pearson Education, Inc., aug 2002,
vol. VI.
[1] S. Kim, T. Shim, and J. Park, "Electrical behavior of ultra-thin body
silicon-on-insulator n-mosfets at a high operating temperaure," Journal
of Ceramic Processing Reseach, vol. 10, no. 4, pp. 507 -511, 2009.
[2] Y. Omura, A. Nakakubo, and H. Nakatsuji, "Quantum mechanical
effect in temperature dependence of threshold voltage of extremely
thin soi mosfets," Solid-State Electronics, vol. 48, no. 9, pp. 1661 -
1666, 2004, non Volatile Memories with discrete storage nodes. (Online).
Available: http://www.sciencedirect.com/science/article/B6TY5-
4CDHD5K-2/2/4ce9ebb7270ac96308d1ce7efda02d80
[3] H.-K. Lim and J. Fossum, "Threshold voltage of thin-film siliconon-
insulator (soi) mosfet-s," Electron Devices, IEEE Transactions on,
vol. 30, no. 10, pp. 1244 - 1251, oct 1983.
[4] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono,
Y. Takahashi, and K. Murase, "Ultimately thin double-gate soi mosfets,"
Electron Devices, IEEE Transactions on, vol. 50, no. 3, pp. 830 - 838,
march 2003.
[5] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor,
and C. Hu, "Ultra-thin body soi mosfet for deep-sub-tenth micron era," in
Electron Devices Meeting, 1999. IEDM Technical Digest. International,
1999, pp. 919 -921.
[6] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical
effects on the threshold voltage of ultrathin-soi nmosfets," Electron
Device Letters, IEEE, vol. 14, no. 12, pp. 569 -571, dec 1993.
[7] D. Flandre, A. Terao, P. Francis, B. Gentinne, and J.-P. Colinge,
"Demonstration of the potential of accumulation-mode mos transistors
on soi substrates for high-temperature operation (150-300 deg;c)," Electron
Device Letters, IEEE, vol. 14, no. 1, pp. 10 -12, jan 1993.
[8] G. Groeseneken, J.-P. Colinge, H. Maes, J. Alderman, and S. Holt,
"Temperature dependence of threshold voltage in thin-film soi mosfets,"
Electron Device Letters, IEEE, vol. 11, no. 8, pp. 329 -331, aug 1990.
[9] M. Shams, M. Alam, and Q. Khosru, "Effect of uniaxial strain on the
gate capacitance of double gate mosfets," in Electron Devices and Solid-
State Circuits, 2008. EDSSC 2008. IEEE International Conference on,
Dec 2008, pp. 1 -4.
[10] M. Shams, K. Habib, R. Mikail, Q. D. M. Khosru, A. Zainuddin,
and A. Haque, "An improved physically based compact c-v model for
mos devices with high-k gate dielectrics," in Electrical and Computer
Engineering, 2006. ICECE -06. International Conference on, 19-21
2006, pp. 518 -521.
[11] S. Ahmed, Ahsan-Ul-Alam, M. Alam, and Q. Khosru, "Gate leakage
current of a double gate n-mos on (111) silicon - a quantum mechanical
study," in Computer and Communication Engineering, 2008. ICCCE
2008. International Conference on, 13-15 2008, pp. 960 -963.
[12] B. Afzal, A. Zahabi, A. Amirabadi, Y. Koolivand, A. Afzali-
Kusha, and M. E. Nokali, "Analytical model for c-v characteristic
of fully depleted soi-mos capacitors," Solid-State Electronics,
vol. 49, no. 8, pp. 1262 - 1273, 2005. (Online). Available:
http://www.sciencedirect.com/science/article/B6TY5-4GSJXNG-
1/2/b2e3fd3db337369e3dac71c3cf389f3f
[13] F. Ikraiam, R. Beck, and A. Jakubowski, "Modeling of soi-mos capacitors
c-v behavior: partially- and fully-depleted cases," Electron Devices,
IEEE Transactions on, vol. 45, no. 5, pp. 1026 -1032, may 1998.
[14] S. C. Rustagi, Z. O. Mohsen, S. Chandra, and A. Chand,
"C-v characterization of mos capacitors in soi structures," Solid-
State Electronics, vol. 39, no. 6, pp. 841 - 849, 1996. (Online).
Available: http://www.sciencedirect.com/science/article/B6TY5-
3VTNT9C-19/2/f30b05629516edb8750425d53140d77e
[15] A. Haque and M. Kauser, "A comparison of wave-function penetration
effects on gate capacitance in deep submicron n- and p-mosfets,"
Electron Devices, IEEE Transactions on, vol. 49, no. 9, pp. 1580 -
1587, sep 2002.
[16] N. Weste, D. Harris, and A. Banarjee, CMOS VLSI Design : A Circuits
and Systems Perspective, 3rd ed. USA: Pearson Education Inc., 2008.
[17] L. Chang, K. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu,
"Direct-tunneling gate leakage current in double-gate and ultrathin body
mosfets," Electron Devices, IEEE Transactions on, vol. 49, no. 12, pp.
2288 - 2295, dec 2002.
[18] S. Sze and K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken,
NJ, USA: John Wiley & Sons, Inc., April 2006.
[19] R. F. Pierret, Advanced Semiconductor Fundamentals, 2nd ed., ser.
Modular Series on Solid State Devices, R. Pierret and G. Neudeck,
Eds. Upper Saddle River, NJ, USA: Pearson Education, Inc., aug 2002,
vol. VI.
@article{"International Journal of Electrical, Electronic and Communication Sciences:54163", author = "Shuvro Chowdhury and Esmat Farzana and Rizvi Ahmed and A. T. M. Golam Sarwar and M. Ziaur Rahman Khan", title = "C-V Characterization and Analysis of Temperature and Channel Thickness Effects on Threshold Voltage of Ultra-thin SOI MOSFET by Self-Consistent Model", abstract = "The threshold voltage and capacitance voltage characteristics of ultra-thin Silicon-on-Insulator MOSFET are greatly influenced by the thickness and doping concentration of the silicon film. In this work, the capacitance voltage characteristics and threshold voltage of the device have been analyzed with quantum mechanical effects using the Self-Consistent model. Reduction of channel thickness and adding doping impurities cause an increase in the threshold voltage. Moreover, the temperature effects cause a significant amount of threshold voltage shift. The temperature dependence of threshold voltage has also been observed with Self- Consistent approach which are well supported from experimental performance of practical devices.
", keywords = "C-V characteristics, Self-Consistent Analysis, Siliconon-Insulator, Ultra-thin film.", volume = "4", number = "9", pages = "1362-6", }
