Average Current Estimation Technique for Reliability Analysis of Multiple Semiconductor Interconnects
Average current analysis checking the impact of
current flow is very important to guarantee the reliability of
semiconductor systems. As semiconductor process technologies
improve, the coupling capacitance often become bigger than self
capacitances. In this paper, we propose an analytic technique for
analyzing average current on interconnects in multi-conductor
structures. The proposed technique has shown to yield the acceptable
errors compared to HSPICE results while providing computational
efficiency.
[1] P. P. Sotiriadis and A. Chandrakasan, "Reducing bus delay in submicron
technology using coding," in Proc. Asia South Pacific Design Automation
Conference, 2001, pp. 109-114.
[2] Chunjie Duan, Anup Tirumala and S. P. Khatri, "Analysis and avoidance
of cross-talk in on-chip buses," Hot Interconnects 9, 2001, pp. 133-138.
[3] S. R. Sridhara, A. Ahmed and N. R. Shanbhag, "Area and energy-efficient
crosstalk avoidance codes for on-chip buses," in Proc. IEEE International
Conference on Computer Design : VLSI in Computers and Processors, pp.
12-17, 2004.
[4] B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in
Proc. IEEE/ACM International Conference on Computer-Aided Design,
2001, pp. 57-63.
[5] Y. S. Shin and T. Sakurai, "Coupling-driven bus design for low-power
application-specific systems," in Proc. ACM/IEEE Design Automation
Conference, 2001, pp. 750-753.
[6] R. Kumar, "Interconnect and Noise Design for the Pentium 4 Processor,"
Intel Technology Journal Q1, 2001.
[7] M. Celik, L. Pileggi and A. Odabasioglu, IC Interconnect Analysis,
Kluwer Academic Publishers, 2002.
[8] L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for
Timing Analysis," IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 9, 1990, pp. 352-366.
[9] L. T. Pillage, R. A. Rohrer and C. Visweswariah, Electronic Circuit and
System Simulation Methods, McGraw-Hill, Inc., 1994.
[10] K. Agarwal and F. Liu, "Efficient Computation of Current Flow in Signal
Wires for Reliability Analysis," in Proc. IEEE/ACM International
Conference on Computer-Aided Design, 2007, pp. 741-746.
[11] www.public.itrs.net.
[1] P. P. Sotiriadis and A. Chandrakasan, "Reducing bus delay in submicron
technology using coding," in Proc. Asia South Pacific Design Automation
Conference, 2001, pp. 109-114.
[2] Chunjie Duan, Anup Tirumala and S. P. Khatri, "Analysis and avoidance
of cross-talk in on-chip buses," Hot Interconnects 9, 2001, pp. 133-138.
[3] S. R. Sridhara, A. Ahmed and N. R. Shanbhag, "Area and energy-efficient
crosstalk avoidance codes for on-chip buses," in Proc. IEEE International
Conference on Computer Design : VLSI in Computers and Processors, pp.
12-17, 2004.
[4] B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in
Proc. IEEE/ACM International Conference on Computer-Aided Design,
2001, pp. 57-63.
[5] Y. S. Shin and T. Sakurai, "Coupling-driven bus design for low-power
application-specific systems," in Proc. ACM/IEEE Design Automation
Conference, 2001, pp. 750-753.
[6] R. Kumar, "Interconnect and Noise Design for the Pentium 4 Processor,"
Intel Technology Journal Q1, 2001.
[7] M. Celik, L. Pileggi and A. Odabasioglu, IC Interconnect Analysis,
Kluwer Academic Publishers, 2002.
[8] L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for
Timing Analysis," IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 9, 1990, pp. 352-366.
[9] L. T. Pillage, R. A. Rohrer and C. Visweswariah, Electronic Circuit and
System Simulation Methods, McGraw-Hill, Inc., 1994.
[10] K. Agarwal and F. Liu, "Efficient Computation of Current Flow in Signal
Wires for Reliability Analysis," in Proc. IEEE/ACM International
Conference on Computer-Aided Design, 2007, pp. 741-746.
[11] www.public.itrs.net.
@article{"International Journal of Information, Control and Computer Sciences:49649", author = "Ki-Young Kim and Jae-Ho Lim and Deok-Min Kim and Seok-Yoon Kim", title = "Average Current Estimation Technique for Reliability Analysis of Multiple Semiconductor Interconnects", abstract = "Average current analysis checking the impact of
current flow is very important to guarantee the reliability of
semiconductor systems. As semiconductor process technologies
improve, the coupling capacitance often become bigger than self
capacitances. In this paper, we propose an analytic technique for
analyzing average current on interconnects in multi-conductor
structures. The proposed technique has shown to yield the acceptable
errors compared to HSPICE results while providing computational
efficiency.", keywords = "current moment, interconnect modeling, reliability
analysis, worst-case switching", volume = "4", number = "11", pages = "1636-5", }