A High Level Implementation of a High Performance Data Transfer Interface for NoC
The distribution of a single global clock across a chip
has become the major design bottleneck for high performance VLSI
systems owing to the power dissipation, process variability and multicycle
cross-chip signaling. A Network-on-Chip (NoC) architecture
partitioned into several synchronous blocks has become a promising
approach for attaining fine-grain power management at the system
level. In a NoC architecture the communication between the blocks is
handled asynchronously. To interface these blocks on a chip
operating at different frequencies, an asynchronous FIFO interface is
inevitable. However, these asynchronous FIFOs are not required if
adjacent blocks belong to the same clock domain. In this paper, we
have designed and analyzed a 16-bit asynchronous micropipelined
FIFO of depth four, with the awareness of place and route on an
FPGA device. We have used a commercially available Spartan 3
device and designed a high speed implementation of the
asynchronous 4-phase micropipeline. The asynchronous FIFO
implemented on the FPGA device shows 76 Mb/s throughput and a
handshake cycle of 109 ns for write and 101.3 ns for read at the
simulation under the worst case operating conditions (voltage =
0.95V) on a working chip at the room temperature.
[1] Semiconductor Industry Association, International Technology
Roadmap for Semiconductor, 2009.
[2] Hauck S., Burns S., Borriello G., Ebeling C. An FPGA for implementing
asynchronous circuits. IEEE Design and Test of Computers 11 1994; 3:
60-69.
[3] Royal A, Cheung PYK 2003, Globally asynchronous locally
synchronous FPGA architectures, 13th International Conference on
Field-Programmable Logic and Applications (FPL 2003), SPRINGERVERLAG
BERLIN, Berlin, Pages:355-364, ISSN:0302-9743
[4] LaFrieda, C., Hill, B., Manohar, R.: An Asynchronous FPGA with Two-
Phase Enable-ScaledRouting. In: Proc. Of IEEE International
Symposium on Asynchronous Circuits and Systems; May 2010.
[5] Brunvand, E., Michell, M., Smith, K. A comparison of self-timed design
using FPGA, CMOS,and GaAs technologies. In: Proc. of International
Conf. Computer Design; October1992: pp. 76-80.
[6] Seung-JoonLee, Deok-Young Lee, Young-WoongKo, Jeong-Gun Lee.
Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study.
Communications in Computer and Information Science 2012; vol. 310;
Springer.
[7] Chelsea, T., and Nowick, S. (2004), ‘Robust Interfaces for Mixed
Timing Systems’, IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, 12, 857-873.
[8] Teehan, P., Greenstreet, M., and Lemieux, G. A Survey and Taxonomy
of GALS Design Styles. IEEE Design and Test of Computers 2007; 24:
pp. 418-428. [9] X. Wang, D.Sigüenza-Tortosa, T. Ahonen, and J. Nurmi. Asynchronous
Node Design for Network-On- Chip. Proceedings of 2005 International
Symposium on Signal Circuits and System; July 2005.
[10] I.E. Sutherland. Micropipelines. Communication of the ACM; June
1989vol. 32; no. 6: pp 720-738.
[11] Brunvand, “Low latency self-timed flow-through FIFOs”, Proceedings
of Sixteenth Conference on Advanced Research in VLSI, pp.76 – 90,
March 1995.
[12] A.V. Yakovlev, A.M. Koelmans, and L. Lavagno. High-Level Modeling
and Design of Asynchronous Interface Logic. IEEE Design and Test of
Computers; Spring 1995.
[13] T. Chelcea, and S.M. Nowick. Low-latency asynchronous FIFO's using
token rings. Proceedings of SixthInternational Symposium on Advanced
Research in AsynchronousCircuits and Systems; April 2000: pp. 210 –
220.
[14] K.K. Yi. The Design of a Self–Timed Low Power FIFO Using a Word–
Slice Structure. M.Phil, University of Manchester, September 1998.
[15] Xin Wang, Jari Nurmi. A RTL Asynchronous FIFO Design Using
Modified Micropipeline. The10th Biennial Baltic Electronic Conference
(BEC 2006), Estonia; October 2006.
[16] P.day, J.V. Woods. Investigation into Micropipeline Latch Design
Styles. IEEE Transaction on VLSI Sytems ,Vol. 3; 1995.
[17] Xilinx, ISE Design Software Manuals and Help. Sept, 2010
[1] Semiconductor Industry Association, International Technology
Roadmap for Semiconductor, 2009.
[2] Hauck S., Burns S., Borriello G., Ebeling C. An FPGA for implementing
asynchronous circuits. IEEE Design and Test of Computers 11 1994; 3:
60-69.
[3] Royal A, Cheung PYK 2003, Globally asynchronous locally
synchronous FPGA architectures, 13th International Conference on
Field-Programmable Logic and Applications (FPL 2003), SPRINGERVERLAG
BERLIN, Berlin, Pages:355-364, ISSN:0302-9743
[4] LaFrieda, C., Hill, B., Manohar, R.: An Asynchronous FPGA with Two-
Phase Enable-ScaledRouting. In: Proc. Of IEEE International
Symposium on Asynchronous Circuits and Systems; May 2010.
[5] Brunvand, E., Michell, M., Smith, K. A comparison of self-timed design
using FPGA, CMOS,and GaAs technologies. In: Proc. of International
Conf. Computer Design; October1992: pp. 76-80.
[6] Seung-JoonLee, Deok-Young Lee, Young-WoongKo, Jeong-Gun Lee.
Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study.
Communications in Computer and Information Science 2012; vol. 310;
Springer.
[7] Chelsea, T., and Nowick, S. (2004), ‘Robust Interfaces for Mixed
Timing Systems’, IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, 12, 857-873.
[8] Teehan, P., Greenstreet, M., and Lemieux, G. A Survey and Taxonomy
of GALS Design Styles. IEEE Design and Test of Computers 2007; 24:
pp. 418-428. [9] X. Wang, D.Sigüenza-Tortosa, T. Ahonen, and J. Nurmi. Asynchronous
Node Design for Network-On- Chip. Proceedings of 2005 International
Symposium on Signal Circuits and System; July 2005.
[10] I.E. Sutherland. Micropipelines. Communication of the ACM; June
1989vol. 32; no. 6: pp 720-738.
[11] Brunvand, “Low latency self-timed flow-through FIFOs”, Proceedings
of Sixteenth Conference on Advanced Research in VLSI, pp.76 – 90,
March 1995.
[12] A.V. Yakovlev, A.M. Koelmans, and L. Lavagno. High-Level Modeling
and Design of Asynchronous Interface Logic. IEEE Design and Test of
Computers; Spring 1995.
[13] T. Chelcea, and S.M. Nowick. Low-latency asynchronous FIFO's using
token rings. Proceedings of SixthInternational Symposium on Advanced
Research in AsynchronousCircuits and Systems; April 2000: pp. 210 –
220.
[14] K.K. Yi. The Design of a Self–Timed Low Power FIFO Using a Word–
Slice Structure. M.Phil, University of Manchester, September 1998.
[15] Xin Wang, Jari Nurmi. A RTL Asynchronous FIFO Design Using
Modified Micropipeline. The10th Biennial Baltic Electronic Conference
(BEC 2006), Estonia; October 2006.
[16] P.day, J.V. Woods. Investigation into Micropipeline Latch Design
Styles. IEEE Transaction on VLSI Sytems ,Vol. 3; 1995.
[17] Xilinx, ISE Design Software Manuals and Help. Sept, 2010
@article{"International Journal of Information, Control and Computer Sciences:69804", author = "Mansi Jhamb and R. K. Sharma and A. K. Gupta", title = "A High Level Implementation of a High Performance Data Transfer Interface for NoC", abstract = "The distribution of a single global clock across a chip
has become the major design bottleneck for high performance VLSI
systems owing to the power dissipation, process variability and multicycle
cross-chip signaling. A Network-on-Chip (NoC) architecture
partitioned into several synchronous blocks has become a promising
approach for attaining fine-grain power management at the system
level. In a NoC architecture the communication between the blocks is
handled asynchronously. To interface these blocks on a chip
operating at different frequencies, an asynchronous FIFO interface is
inevitable. However, these asynchronous FIFOs are not required if
adjacent blocks belong to the same clock domain. In this paper, we
have designed and analyzed a 16-bit asynchronous micropipelined
FIFO of depth four, with the awareness of place and route on an
FPGA device. We have used a commercially available Spartan 3
device and designed a high speed implementation of the
asynchronous 4-phase micropipeline. The asynchronous FIFO
implemented on the FPGA device shows 76 Mb/s throughput and a
handshake cycle of 109 ns for write and 101.3 ns for read at the
simulation under the worst case operating conditions (voltage =
0.95V) on a working chip at the room temperature.", keywords = "Asynchronous, FIFO, FPGA, GALS, Network-on-
Chip (NoC), VHDL.", volume = "8", number = "10", pages = "1943-6", }