Compaction testing methods allow at-speed detecting
of errors while possessing low cost of implementation. Owing to this
distinctive feature, compaction methods have been widely used for
built-in testing, as well as external testing. In the latter case, the
bandwidth requirements to the automated test equipment employed
are relaxed which reduces the overall cost of testing. Concurrent
compaction testing methods use operational signals to detect
misbehavior of the device under test and do not require input test
stimuli. These methods have been employed for digital systems only.
In the present work, we extend the use of compaction methods for
concurrent testing of analog-to-digital converters. We estimate
tolerance bounds for the result of compaction and evaluate the
aliasing rate.
[1] Actel Corporation, SmartFusion Intelligent Mixed-Signal FPGAs:
Innovative Intelligent Integration, 2010; www. actel. com/ FPGA/ Smart
Fusion
[2] I.Voyiatzis, A. Paschalis, D.Gizopoulos,N.Kranitis, and C.Halatsis, "A
Concurrent BIST Architecture Based on a Self-Testing RAM", IEEE
Transactions on Reliability, vol.54, No.1, 2005, pp. 69-78.
[3] C. Stroude, J. Morton, T. Islam and H. Alassaly, "A mixed-signal built-in
self-test approach for analog circuits", Southwest Symposium on Mixed-
Signal Design, Las Vegas, USA, 2003, pp. 196-201.
[4] R. Frohwerk, "Signature Analysis: A New Digital Field Service
Method",Hewlett Packard J., vol. 28, No 9, May 1977, pp. 2-8.
[5] G. Starr, J. Qin, B. Dutton, C. Stroud, F. Dai and V. Nelson "Automated
generation of built-in self-test and measurement circuitry for mixedsignal
circuits and systems," Proc. IEEE Int. Symp. on Defect and Fault
Tolerance in VLSI Systems, 2009, pp. 11-19.
[6] R. Sharma and K. Saluja, "Theory, analysis and implementation of an
on-line BIST technique," VLSI Design, vol. 1, no 1, 1993, pp. 9-22.
[7] I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, F. Makri, and M.
Hatzimihail, "An input vector monitoring concurrent BIST architecture
based on a precomputed test set," IEEE Trans. Computers, vol. 57, no.
8, 2008, pp. 1012-1022.
[8] I. Voyiatzis, D. Gizopoulos, and A. Paschalis, "An input vector
monitoring concurrent BIST scheme exploiting "X" values," 15th IEEE
Int. On-Line Testing Symposium, 2009, pp. 206-207.
[9] Y.-S. Wang, J.-X.Wang, F.-C.Lai and Y.-Z. Ye, "A low-cost BIST
scheme for ADC testing", Shanghai, China, VI Int. Conf. on ASIC, vol.
2, 2005, pp. 665-668.
[10] D. Lee, K. Yoo, K. Kim, G. Han and S. Kang, "Code-width testingbased
compact ADC BIST circuit", IEEE Trans. on Circuits and
Systems-II: Express briefs, vol. 51, No 11, 2004, pp. 603-606.
[11] G. Wu, J. Rao, A. Ren and M. Ling, "Implementation of a BIST scheme
for ADC test", V Int. Conf. on ASIC, Beijing, China, vol. 2, 2003, pp.
1128-1131.
[12] A. Gookin, "A fast reading high resolution voltmeter that calibrates
itself automatically", Hewlett Packard J., vol. 28, No 6, 1977, pp. 2-10.
[13] V. Kneller, "Measurement, control and other processes: to the problem
of knowledge systematization",Cavtat-Dubrovnik, Croatia, XVII IMEKO
World Congress, 2003, pp. 1119-1124.
[14] G. D'Antona and A. Ferrero, Digital Signal Processing for Measurement
Systems, Springer Science + Business Media Inc., Berlin, 2006.
[15] J. Wakerly, Error Detecting Codes, Self-Checking Circuits and
Applications, Elsevier North-Holland, New York, 1978.
[16] V. Geurkov, L. Kirischian, and V. Kirischian "Signature Testing of
Analog-to-Digital Converters". Proceedings of the 19th IMEKO World
Congress: Fundamental and Applied Metrology, Lisbon,
[1] Actel Corporation, SmartFusion Intelligent Mixed-Signal FPGAs:
Innovative Intelligent Integration, 2010; www. actel. com/ FPGA/ Smart
Fusion
[2] I.Voyiatzis, A. Paschalis, D.Gizopoulos,N.Kranitis, and C.Halatsis, "A
Concurrent BIST Architecture Based on a Self-Testing RAM", IEEE
Transactions on Reliability, vol.54, No.1, 2005, pp. 69-78.
[3] C. Stroude, J. Morton, T. Islam and H. Alassaly, "A mixed-signal built-in
self-test approach for analog circuits", Southwest Symposium on Mixed-
Signal Design, Las Vegas, USA, 2003, pp. 196-201.
[4] R. Frohwerk, "Signature Analysis: A New Digital Field Service
Method",Hewlett Packard J., vol. 28, No 9, May 1977, pp. 2-8.
[5] G. Starr, J. Qin, B. Dutton, C. Stroud, F. Dai and V. Nelson "Automated
generation of built-in self-test and measurement circuitry for mixedsignal
circuits and systems," Proc. IEEE Int. Symp. on Defect and Fault
Tolerance in VLSI Systems, 2009, pp. 11-19.
[6] R. Sharma and K. Saluja, "Theory, analysis and implementation of an
on-line BIST technique," VLSI Design, vol. 1, no 1, 1993, pp. 9-22.
[7] I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, F. Makri, and M.
Hatzimihail, "An input vector monitoring concurrent BIST architecture
based on a precomputed test set," IEEE Trans. Computers, vol. 57, no.
8, 2008, pp. 1012-1022.
[8] I. Voyiatzis, D. Gizopoulos, and A. Paschalis, "An input vector
monitoring concurrent BIST scheme exploiting "X" values," 15th IEEE
Int. On-Line Testing Symposium, 2009, pp. 206-207.
[9] Y.-S. Wang, J.-X.Wang, F.-C.Lai and Y.-Z. Ye, "A low-cost BIST
scheme for ADC testing", Shanghai, China, VI Int. Conf. on ASIC, vol.
2, 2005, pp. 665-668.
[10] D. Lee, K. Yoo, K. Kim, G. Han and S. Kang, "Code-width testingbased
compact ADC BIST circuit", IEEE Trans. on Circuits and
Systems-II: Express briefs, vol. 51, No 11, 2004, pp. 603-606.
[11] G. Wu, J. Rao, A. Ren and M. Ling, "Implementation of a BIST scheme
for ADC test", V Int. Conf. on ASIC, Beijing, China, vol. 2, 2003, pp.
1128-1131.
[12] A. Gookin, "A fast reading high resolution voltmeter that calibrates
itself automatically", Hewlett Packard J., vol. 28, No 6, 1977, pp. 2-10.
[13] V. Kneller, "Measurement, control and other processes: to the problem
of knowledge systematization",Cavtat-Dubrovnik, Croatia, XVII IMEKO
World Congress, 2003, pp. 1119-1124.
[14] G. D'Antona and A. Ferrero, Digital Signal Processing for Measurement
Systems, Springer Science + Business Media Inc., Berlin, 2006.
[15] J. Wakerly, Error Detecting Codes, Self-Checking Circuits and
Applications, Elsevier North-Holland, New York, 1978.
[16] V. Geurkov, L. Kirischian, and V. Kirischian "Signature Testing of
Analog-to-Digital Converters". Proceedings of the 19th IMEKO World
Congress: Fundamental and Applied Metrology, Lisbon,
@article{"International Journal of Electrical, Electronic and Communication Sciences:59729", author = "Y.B.Gandole", title = "Concurrent Testing of ADC for Embedded System", abstract = "Compaction testing methods allow at-speed detecting
of errors while possessing low cost of implementation. Owing to this
distinctive feature, compaction methods have been widely used for
built-in testing, as well as external testing. In the latter case, the
bandwidth requirements to the automated test equipment employed
are relaxed which reduces the overall cost of testing. Concurrent
compaction testing methods use operational signals to detect
misbehavior of the device under test and do not require input test
stimuli. These methods have been employed for digital systems only.
In the present work, we extend the use of compaction methods for
concurrent testing of analog-to-digital converters. We estimate
tolerance bounds for the result of compaction and evaluate the
aliasing rate.", keywords = "Analog-to Digital Converter, Embedded system,
Concurrent Testing", volume = "5", number = "11", pages = "1548-4", }