Proposal for a Ultra Low Voltage NAND gate to withstand Power Analysis Attacks

In this paper we promote the Ultra Low Voltage (ULV) NAND gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack.





References:
[1] P. Kocher, J. Jaffe, B. Jun. "Differential Power Analysis". The
Proceedings of CRYPTO -99, Lecture Notes in Computer Science,
2779:17-30, 1999.
[2] P. Kocher. "Timinig Attacks on Implementations of Diffie-Hellman,
RSA, DSS and other systems". Advances in Cryptology CRYPTO-96,
Lecture Notes in Computer Science, 1109:104-113, 1996.
[3] J. Quisquater, D. Samyde. "ElectroMagnetic analysis (EMA): Measures
and Counter-Measures for Smart Cards". Proceedings of the International
Conference on Research in Smart Cards: Smart Card Programming
and Security, Lecture Notes in Computer Science, 2140:200-210,
2001.
[4] K. Tiri, M. Akmal and I. Verbauwhede. "A Dynamic and Differential
CMOS Logic with Signal Independent Power Consumption to Withstand
Differential Power Analysis on Smart Cards". Proceedings of 28th
European Solid-State Circuits Conference (ESSCIRC), pages 403-406,
2002.
[5] K. Tiri and I. Verbauwhede. "A Logic Level Design Methodology for
a Secure DPA Resistant ASIC or FPGA Implementation". Proceedings
of Design Automation and Test in Europe Conference and Exhibition,
1:246-251, 2004.
[6] T. Sundstrom and A. Alvandpour. "A Comparative analysis of logic
styles for secure IC-s against DPA attacks". IEEE Proceedings of
NORCHIP Conference, pages 1-4, November 2005.
[7] Y. Berg, D. T. Wisland and T. S. Lande. "Ultra Low-Voltage/Low-
Power Digital Floating-Gate Circuits". IEEE Transactions on Circuits
and Systems, 46(7):930-936, July 1996.
[8] Y. Berg, O. Mirmotahari, P.A. Norseng and S. Aunet. "Ultra Low Voltage
CMOS Gate". IEEE International Conference on Electronics, Circuits
and System (ICECS), pages 818-821, Desember 2006.
[9] O. Mirmotahari and Y. Berg. "Low Voltage Design against Power
Analysis Attacks". Submitted to VLSI DESIGN 2007, page 1, 1 1.
[10] S. Aunet, Y. Berg, O. Tjore, Ø. N æss, T. Sæther. "Four-MOSFET
Floating-Gate UV-Programmable Elements for Multifunction Binary
Logic". Proceedings of the 5th World Multiconference on Systemics,
Cybernetics and Informatics (SCI), 3:141-144, July 2001.
[11] B. Tongprasit, T.Shibata. "Power-balanced reconfigurable floating-gate-
MOS logic circuit for tamper resistant VLSI". IEEE International
Symposium on Circuits and Systems (ISCAS), pages 21-24, May 2006.