Performance Comparison of Real Time EDAC Systems for Applications On-Board Small Satellites
On-board Error Detection and Correction (EDAC)
devices aim to secure data transmitted between the central
processing unit (CPU) of a satellite onboard computer and its local
memory. This paper presents a comparison of the performance of
four low complexity EDAC techniques for application in Random
Access Memories (RAMs) on-board small satellites. The
performance of a newly proposed EDAC architecture is measured
and compared with three different EDAC strategies, using the same
FPGA technology. A statistical analysis of single-event upset (SEU)
and multiple-bit upset (MBU) activity in commercial memories
onboard Alsat-1 is given for a period of 8 years
[1] Y. Bentoutou, "A Real Time Low Complexity Codec for use in Low
Earth Orbit Small Satellite Missions", IEEE Trans. Nucl. Sci., vol. 53,
no. 3, part 1, pp. 1022-1027, 2006.
[2] Y. Bentoutou, M. Djaifri, A.M. Si Mohammed, "Design and
Implementation of a quasi-cyclic Codec for Random Access Memories
on board Alsat-1", Acta Astronautica, Elsevier Science, vol. 66, no. 5-
6, pages: 954-961, March/April 2010.
[3] Y. Bentoutou, "A Real Time EDAC System for Applications On-
Board Earth Observation Small Satellites", accepted for publication in
IEEE Transactions on Aerospace and Electronic Systems, In press
2011.
[4] M.S. Hodgart, "Efficient Coding and Error Monitoring for Spacecraft
Digital Memory", Int. J. Electronics, vol. 73, no. 1, pp. 1-36, 1992.
[5] M.S. Hodgart and H. Tiggeler, "A (16,8) Error Correcting Code (t=2)
for Critical Memory Applications", in proc. Data Systems In
Aerospace, Montreal, Canada, May 22-26, 2000.
[6] A. Wicks, A. da Silva-Curiel, J. Ward, and M. Fouquet, "Advancing
Small Satellite Earth Observation: Operational Spacecraft, Planned
Missions and Future Concepts", in Proc. 14th Annual AIAA/USU
Conference on Small Satellites, Logan, UT, Aug. 21-24, 2000.
[7] M. Bekhti, M. Sweeting, and W. Sun, "Alsat-1: The first step into
space for Algeria", in Proc. 53 rd IAC and World Space Congress,
Houston, TX, 2002, pp. 10-19.
[8] R.L. Townsend and E.J. Weldon, "Self-orthogonal quasicyclic codes",
IEEE Trans. Inform. Theory, vol. IT-13, no. 2, pp. 183-195, Apr. 1967.
[9] Y. Bentoutou and M. Djaifri, "Observations of Single-Event Upsets
and Multiple-Bit Upsets in Random Access Memories On-Board the
Algerian Satellite", in 2008 IEEE Nuclear Science Symposium
Conference Record, Edited by Paul Sellin, Oct. 2008, pp. 2568-2570.
[1] Y. Bentoutou, "A Real Time Low Complexity Codec for use in Low
Earth Orbit Small Satellite Missions", IEEE Trans. Nucl. Sci., vol. 53,
no. 3, part 1, pp. 1022-1027, 2006.
[2] Y. Bentoutou, M. Djaifri, A.M. Si Mohammed, "Design and
Implementation of a quasi-cyclic Codec for Random Access Memories
on board Alsat-1", Acta Astronautica, Elsevier Science, vol. 66, no. 5-
6, pages: 954-961, March/April 2010.
[3] Y. Bentoutou, "A Real Time EDAC System for Applications On-
Board Earth Observation Small Satellites", accepted for publication in
IEEE Transactions on Aerospace and Electronic Systems, In press
2011.
[4] M.S. Hodgart, "Efficient Coding and Error Monitoring for Spacecraft
Digital Memory", Int. J. Electronics, vol. 73, no. 1, pp. 1-36, 1992.
[5] M.S. Hodgart and H. Tiggeler, "A (16,8) Error Correcting Code (t=2)
for Critical Memory Applications", in proc. Data Systems In
Aerospace, Montreal, Canada, May 22-26, 2000.
[6] A. Wicks, A. da Silva-Curiel, J. Ward, and M. Fouquet, "Advancing
Small Satellite Earth Observation: Operational Spacecraft, Planned
Missions and Future Concepts", in Proc. 14th Annual AIAA/USU
Conference on Small Satellites, Logan, UT, Aug. 21-24, 2000.
[7] M. Bekhti, M. Sweeting, and W. Sun, "Alsat-1: The first step into
space for Algeria", in Proc. 53 rd IAC and World Space Congress,
Houston, TX, 2002, pp. 10-19.
[8] R.L. Townsend and E.J. Weldon, "Self-orthogonal quasicyclic codes",
IEEE Trans. Inform. Theory, vol. IT-13, no. 2, pp. 183-195, Apr. 1967.
[9] Y. Bentoutou and M. Djaifri, "Observations of Single-Event Upsets
and Multiple-Bit Upsets in Random Access Memories On-Board the
Algerian Satellite", in 2008 IEEE Nuclear Science Symposium
Conference Record, Edited by Paul Sellin, Oct. 2008, pp. 2568-2570.
@article{"International Journal of Information, Control and Computer Sciences:58457", author = "Y. Bentoutou", title = "Performance Comparison of Real Time EDAC Systems for Applications On-Board Small Satellites", abstract = "On-board Error Detection and Correction (EDAC)
devices aim to secure data transmitted between the central
processing unit (CPU) of a satellite onboard computer and its local
memory. This paper presents a comparison of the performance of
four low complexity EDAC techniques for application in Random
Access Memories (RAMs) on-board small satellites. The
performance of a newly proposed EDAC architecture is measured
and compared with three different EDAC strategies, using the same
FPGA technology. A statistical analysis of single-event upset (SEU)
and multiple-bit upset (MBU) activity in commercial memories
onboard Alsat-1 is given for a period of 8 years", keywords = "Error Detection and Correction; On-board
computer; small satellite missions", volume = "5", number = "5", pages = "488-4", }