Development of Manufacturing Simulation Model for Semiconductor Fabrication
This research presents the development of simulation
modeling for WIP management in semiconductor fabrication.
Manufacturing simulation modeling is needed for productivity
optimization analysis due to the complex process flows involved
more than 35 percent re-entrance processing steps more than 15 times
at same equipment. Furthermore, semiconductor fabrication required
to produce high product mixed with total processing steps varies from
300 to 800 steps and cycle time between 30 to 70 days. Besides the
complexity, expansive wafer cost that potentially impact the
company profits margin once miss due date is another motivation to
explore options to experiment any analysis using simulation
modeling. In this paper, the simulation model is developed using
existing commercial software platform AutoSched AP, with
customized integration with Manufacturing Execution Systems
(MES) and Advanced Productivity Family (APF) for data collections
used to configure the model parameters and data source. Model
parameters such as processing steps cycle time, equipment
performance, handling time, efficiency of operator are collected
through this customization. Once the parameters are validated, few
customizations are made to ensure the prior model is executed. The
accuracy for the simulation model is validated with the actual output
per day for all equipments. The comparison analysis from result of
the simulation model compared to actual for achieved 95 percent
accuracy for 30 days. This model later was used to perform various
what if analysis to understand impacts on cycle time and overall
output. By using this simulation model, complex manufacturing
environment like semiconductor fabrication (fab) now have
alternative source of validation for any new requirements impact
analysis.
[1] Moti Klein and Adar Kalir," A Full Factory transient Simulation model
For The Analysis of Expected Performance in A Transition Period," in
Proc. winter simulation Conf .Israel, 2006.
[2] Boon Ping Gan, Peter Lendermann, Malcolm Yoke Hean Low, Stephen
J. Turner, Xiaoguang Wang and Simon J.E. Taylor "Interoperating
AutoSched AP Using The High Level Architecture," in Proc. Winter
Simulation Conf. Singapore, 2005.
[3] Tyler Philips, "AutoSched AP by AutoSimulations," in Proc. Winter
Simulation Conf. U.S.A, 1998.
[4] Ingy A. El-Khouly, Khaled S. El-Kilany, and Aziz E.-Sayed, "Effective
Scheduling of Semiconductor Manufacturing", World Academy of
Science, Engineering and Technology, vol. 79, 2011.
[5] Kader Ibrahim, Mohd Azizi Chik and UdaHashim, "Variability Due to
Tool Configurations That Impacts Overall Capacity in Wafer
Fabrication Facility" The 11th Asia Pacific Industrial Engineering and
Management Systems Conference, Melaka, 2010.
[6] YudhaAndrianSaputra&StefanusEkoW.,"Combination of MAPE,
MedAPE, and Skewness of APE", Industrial Engineering And Service
Science (IESS) International Conferenc, SOLO.2011.
[7] Ben H. Thacker, Scott W. Doebling, Francois M. Hemez, Mark C.
Anderson, Jason E. Pepin and Edward A. Rodriguez, Concepts of Model
Verification and Validation. California, CA: United States Department
of Energy, 2004, pp.17-21.
[8] Applied AutoSched AP. 2011. AutoSched AP Release Note v 10.0.1.
[9] Global Semiconductor Alliance (GSA), Semiconductor Market
Overview, April 2011.
[10] Mohd Azizi Chik, Mohd Hazmuni bin Saidin, and Uda bin Hashim,
"Industrial Engineering Roles in Semiconductor Fabrication", APIEM
11th Conf. December 2010.
[11] R. C. Leachman, D. A. Hodges, "Benchmarking Semiconductor
Manufacturing," IEEE Trans. on Semiconductor Manufacturing, TSM-9
(May 1996), pp. 158-169.
[12] Mohd Azizi Chik, Yeo EngTeck, Mahalil Amin AbdMalek, and Mohd
HafidzSaidi, "Comprehensive Sequencing Dispatching Method for
Identified Bottleneck Tool - Photolithography Process", NSM, Perlis,
Malaysia, pp.19-21. 2003.
[1] Moti Klein and Adar Kalir," A Full Factory transient Simulation model
For The Analysis of Expected Performance in A Transition Period," in
Proc. winter simulation Conf .Israel, 2006.
[2] Boon Ping Gan, Peter Lendermann, Malcolm Yoke Hean Low, Stephen
J. Turner, Xiaoguang Wang and Simon J.E. Taylor "Interoperating
AutoSched AP Using The High Level Architecture," in Proc. Winter
Simulation Conf. Singapore, 2005.
[3] Tyler Philips, "AutoSched AP by AutoSimulations," in Proc. Winter
Simulation Conf. U.S.A, 1998.
[4] Ingy A. El-Khouly, Khaled S. El-Kilany, and Aziz E.-Sayed, "Effective
Scheduling of Semiconductor Manufacturing", World Academy of
Science, Engineering and Technology, vol. 79, 2011.
[5] Kader Ibrahim, Mohd Azizi Chik and UdaHashim, "Variability Due to
Tool Configurations That Impacts Overall Capacity in Wafer
Fabrication Facility" The 11th Asia Pacific Industrial Engineering and
Management Systems Conference, Melaka, 2010.
[6] YudhaAndrianSaputra&StefanusEkoW.,"Combination of MAPE,
MedAPE, and Skewness of APE", Industrial Engineering And Service
Science (IESS) International Conferenc, SOLO.2011.
[7] Ben H. Thacker, Scott W. Doebling, Francois M. Hemez, Mark C.
Anderson, Jason E. Pepin and Edward A. Rodriguez, Concepts of Model
Verification and Validation. California, CA: United States Department
of Energy, 2004, pp.17-21.
[8] Applied AutoSched AP. 2011. AutoSched AP Release Note v 10.0.1.
[9] Global Semiconductor Alliance (GSA), Semiconductor Market
Overview, April 2011.
[10] Mohd Azizi Chik, Mohd Hazmuni bin Saidin, and Uda bin Hashim,
"Industrial Engineering Roles in Semiconductor Fabrication", APIEM
11th Conf. December 2010.
[11] R. C. Leachman, D. A. Hodges, "Benchmarking Semiconductor
Manufacturing," IEEE Trans. on Semiconductor Manufacturing, TSM-9
(May 1996), pp. 158-169.
[12] Mohd Azizi Chik, Yeo EngTeck, Mahalil Amin AbdMalek, and Mohd
HafidzSaidi, "Comprehensive Sequencing Dispatching Method for
Identified Bottleneck Tool - Photolithography Process", NSM, Perlis,
Malaysia, pp.19-21. 2003.
@article{"International Journal of Mechanical, Industrial and Aerospace Sciences:59363", author = "Syahril Ridzuan Ab Rahim and Ibrahim Ahmad and Mohd Azizi Chik and Ahmad Zafir Md. Rejab and and
U. Hashim", title = "Development of Manufacturing Simulation Model for Semiconductor Fabrication", abstract = "This research presents the development of simulation
modeling for WIP management in semiconductor fabrication.
Manufacturing simulation modeling is needed for productivity
optimization analysis due to the complex process flows involved
more than 35 percent re-entrance processing steps more than 15 times
at same equipment. Furthermore, semiconductor fabrication required
to produce high product mixed with total processing steps varies from
300 to 800 steps and cycle time between 30 to 70 days. Besides the
complexity, expansive wafer cost that potentially impact the
company profits margin once miss due date is another motivation to
explore options to experiment any analysis using simulation
modeling. In this paper, the simulation model is developed using
existing commercial software platform AutoSched AP, with
customized integration with Manufacturing Execution Systems
(MES) and Advanced Productivity Family (APF) for data collections
used to configure the model parameters and data source. Model
parameters such as processing steps cycle time, equipment
performance, handling time, efficiency of operator are collected
through this customization. Once the parameters are validated, few
customizations are made to ensure the prior model is executed. The
accuracy for the simulation model is validated with the actual output
per day for all equipments. The comparison analysis from result of
the simulation model compared to actual for achieved 95 percent
accuracy for 30 days. This model later was used to perform various
what if analysis to understand impacts on cycle time and overall
output. By using this simulation model, complex manufacturing
environment like semiconductor fabrication (fab) now have
alternative source of validation for any new requirements impact
analysis.", keywords = "Advanced Productivity Family (APF),
Complementary Metal Oxide Semiconductor (CMOS),
Manufacturing Execution Systems (MES), Work In Progress
(WIP).", volume = "7", number = "2", pages = "292-5", }