A new design approach for three-stage operational
amplifiers (op-amps) is proposed. It allows to actually implement a
symmetrical push-pull class-AB amplifier output stage for wellestablished
three-stage amplifiers using a feedforward
transconductance stage. Compared with the conventional design
practice, the proposed approach leads to a significant
improvement of the symmetry between the positive and the
negative op-amp step response, resulting in similar values of the
positive/negative settling time. The new approach proves to be very
useful in order to fully exploit the potentiality allowed by the op-amp
in terms of speed performances. Design examples in a commercial
0.35-μm CMOS prove the effectiveness of theproposed strategy.
[1] S-C. Lee, Y-D. Jeon, J-K. Kwon, and J. Kim, "A 10-bit 205-MS/s 1.0-
mm2 90-nm CMOS Pipeline ADC for flat Panel Display Applications,"
IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688-2695, Dec. 2007.
[2] H. L. Lee, and P. K. T. Mok, "An SC Voltage Doubler with Pseudo-
Continuous Output Regulation Using a Three-Stage Switchable
Opamp", IEEE J. Solid-State Circuits, vol.43, no.6, pp.1216-1229, Jun.
2007.
[3] H.-C. Lin, H.-H. Wu, and T.-Y. Chang, "An Active-Frequency
Compensation Scheme for CMOS Low-Dropout Regulators With
Transient-Response Improvement," IEEE Trans. On Circ. And Syst.
IIExpr. Briefs, vol. 55, no. 9, pp. 853-857, Sep. 2008.
[4] W.-J. Huang S.-I. Liu, "Capacitor-free low dropout regulators using
nested Miller compensation with active resistor and 1-bit programmable
capacitor array," IET Circuits, Devices & Systems, vol. 2, no. 3, pp.
306-316, Mar. 2007.
[5] A.D. Grasso, G. Palumbo, and S. Pennisi, "Analytical comparison of
frequency compensation techniques in three-stage amplifiers," Inter.
Jour. Circ. Theory and Applic., vol. 36, no.1, pp. 53-80, Jan. 2008.
[6] S.O. Cannizzaro, A.D. Grasso, R. Mita, G. Palumbo, S. Pennisi,
"Design procedures for three-stage CMOS OTAs with nested-
Miller compensation," IEEE Trans. Circuits Syst. I, Regul. Papers, vol.
54, no.5, pp. 933-940, May 2007.
[7] R.G.H. Eschauzier and J.H. Huiising, Frequency Compensation
Techniques for Low-Power Operational Amplifier, Boston, M.A.:
Kluwer, 1995.
[8] K.N. Leung, and P.K.T. Mok, "Analysis of multistage amplifierfrequency
compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
[9] Peng, X., and Sansen, W., "Transconductance with capacitances
feedback compensation for multistage amplifiers", IEEE Jour. of Solid-
State Circuits, vol. 40, no. 7, pp. 1514-1520, 2005.
[10] Leung, K.N., Mok, P. K. T., Ki, W.-H., and Sin, J. K. O., "Three-stage
large capacitive load amplifier with damping-factor-control frequency
compensation", IEEE Jour. of Solid-State Circuits, vol. 35, no. 2, pp.
221-230, 2000.
[11] Peng X., and Sansen, W., "AC Boosting Compensation Scheme for
Low-Power Multistage Amplifiers", IEEE Jour. of Solid-State Circuits,
vol. 39, no. 11, pp. 2074-2079, Nov. 2004.
[12] Cannizzaro, S. O., Grasso A. D., Palumbo, G. and Pennisi S., "Single
Miller capacitor frequency compensation with nulling resistor for threestage
amplifiers", Int. Jour. of Circ. Theory and Appl., vol. 36, pp. 825-
837, 2008
[13] A. Pugliese, G. Cappuccino, and G. Cocorullo, "Design Procedure for
Settling Time Minimization in Three-Stage Nested-Miller Amplifiers,"
IEEE Trans. On Circ. And Syt. II- Expr. Briefs, vol. 55, no. 1, pp. 1-5,
Jan. 2008.
[1] S-C. Lee, Y-D. Jeon, J-K. Kwon, and J. Kim, "A 10-bit 205-MS/s 1.0-
mm2 90-nm CMOS Pipeline ADC for flat Panel Display Applications,"
IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688-2695, Dec. 2007.
[2] H. L. Lee, and P. K. T. Mok, "An SC Voltage Doubler with Pseudo-
Continuous Output Regulation Using a Three-Stage Switchable
Opamp", IEEE J. Solid-State Circuits, vol.43, no.6, pp.1216-1229, Jun.
2007.
[3] H.-C. Lin, H.-H. Wu, and T.-Y. Chang, "An Active-Frequency
Compensation Scheme for CMOS Low-Dropout Regulators With
Transient-Response Improvement," IEEE Trans. On Circ. And Syst.
IIExpr. Briefs, vol. 55, no. 9, pp. 853-857, Sep. 2008.
[4] W.-J. Huang S.-I. Liu, "Capacitor-free low dropout regulators using
nested Miller compensation with active resistor and 1-bit programmable
capacitor array," IET Circuits, Devices & Systems, vol. 2, no. 3, pp.
306-316, Mar. 2007.
[5] A.D. Grasso, G. Palumbo, and S. Pennisi, "Analytical comparison of
frequency compensation techniques in three-stage amplifiers," Inter.
Jour. Circ. Theory and Applic., vol. 36, no.1, pp. 53-80, Jan. 2008.
[6] S.O. Cannizzaro, A.D. Grasso, R. Mita, G. Palumbo, S. Pennisi,
"Design procedures for three-stage CMOS OTAs with nested-
Miller compensation," IEEE Trans. Circuits Syst. I, Regul. Papers, vol.
54, no.5, pp. 933-940, May 2007.
[7] R.G.H. Eschauzier and J.H. Huiising, Frequency Compensation
Techniques for Low-Power Operational Amplifier, Boston, M.A.:
Kluwer, 1995.
[8] K.N. Leung, and P.K.T. Mok, "Analysis of multistage amplifierfrequency
compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory
Appl., vol. 48, no. 9, pp. 1041-1056, Sep. 2001.
[9] Peng, X., and Sansen, W., "Transconductance with capacitances
feedback compensation for multistage amplifiers", IEEE Jour. of Solid-
State Circuits, vol. 40, no. 7, pp. 1514-1520, 2005.
[10] Leung, K.N., Mok, P. K. T., Ki, W.-H., and Sin, J. K. O., "Three-stage
large capacitive load amplifier with damping-factor-control frequency
compensation", IEEE Jour. of Solid-State Circuits, vol. 35, no. 2, pp.
221-230, 2000.
[11] Peng X., and Sansen, W., "AC Boosting Compensation Scheme for
Low-Power Multistage Amplifiers", IEEE Jour. of Solid-State Circuits,
vol. 39, no. 11, pp. 2074-2079, Nov. 2004.
[12] Cannizzaro, S. O., Grasso A. D., Palumbo, G. and Pennisi S., "Single
Miller capacitor frequency compensation with nulling resistor for threestage
amplifiers", Int. Jour. of Circ. Theory and Appl., vol. 36, pp. 825-
837, 2008
[13] A. Pugliese, G. Cappuccino, and G. Cocorullo, "Design Procedure for
Settling Time Minimization in Three-Stage Nested-Miller Amplifiers,"
IEEE Trans. On Circ. And Syt. II- Expr. Briefs, vol. 55, no. 1, pp. 1-5,
Jan. 2008.
@article{"International Journal of Electrical, Electronic and Communication Sciences:64474", author = "B.Gholami and S.Gholami and A.Forouzantabar and Sh.Bazyari", title = "Design a Low Voltage- Low Offset Class AB Op-Amp", abstract = "A new design approach for three-stage operational
amplifiers (op-amps) is proposed. It allows to actually implement a
symmetrical push-pull class-AB amplifier output stage for wellestablished
three-stage amplifiers using a feedforward
transconductance stage. Compared with the conventional design
practice, the proposed approach leads to a significant
improvement of the symmetry between the positive and the
negative op-amp step response, resulting in similar values of the
positive/negative settling time. The new approach proves to be very
useful in order to fully exploit the potentiality allowed by the op-amp
in terms of speed performances. Design examples in a commercial
0.35-μm CMOS prove the effectiveness of theproposed strategy.", keywords = "Low-voltage op amp, design , optimum design", volume = "5", number = "6", pages = "780-3", }
