Analysis of CNT Bundle and its Comparison with Copper for FPGAs Interconnects
Each new semiconductor technology node
brings smaller transistors and wires. Although this makes
transistors faster, wires get slower. In nano-scale regime, the
standard copper (Cu) interconnect will become a major hurdle
for FPGA interconnect due to their high resistivity and
electromigration. This paper presents the comprehensive
evaluation of mixed CNT bundle interconnects and
investigates their prospects as energy efficient and high speed
interconnect for future FPGA routing architecture. All
HSPICE simulations are carried out at operating frequency of
1GHz and it is found that mixed CNT bundle implemented in
FPGAs as interconnect can potentially provide a substantial
delay and energy reduction over traditional interconnects at
32nm process technology.
[1] G. Lemieux and D. Lewis, Design of Interconnection Networks for
Programmable Logic, Kluwer Academic Publishers, 2004
[2] F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and
Characteristics of Field Programmable Gate Arrays," TCAD, vol. 24,
[3] A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison
between carbon nanotube and copper interconnects for gigascale
integration (GSI)", IEEE Electron Device Letters, vol. 26, pp. 84-86,
[4] A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison
between carbon nanotube and copper interconnects for gigascale
integration (GSI)," IEEE Electron Device Letters, vol. 26, no. 2, pp. 84-
86, 2005.
[5] N. Srivastava and K. Banerjee, "A comparative scaling analysis
of metallic and carbon nanotube interconnections for nanometer scale
VLSI technologies," in Proceedings of the 21st International VLSI
Multilevel Interconnection Conference (VMIC -04), pp. 393-398, 2004.
[6] A. Raychowdhury and K. Roy, "Modeling of metallic carbonnanotube
interconnects for circuit simulations and a comparison with Cu
interconnects for scaled technologies," IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no.
1, pp. 58-65, 2006.
[7] A. Raychowdhury and K. Roy, "A circuit model for carbon nanotube
interconnects: comparative study with Cu interconnects for scaled
technologies," in Proceedings of IEEE/ACM International Conference
on Computer-Aided Design (ICCAD -04), pp. 237-240, 2004.
[8] P. McEuen, M. Fuhrer, and H. Park, "Single-walled carbon nanotube
electronics," IEEE Transactions on Nanotechnology, vol. 1, no. 1, pp.
78-85, 2002.
[9] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, "Multichannel
ballistic transport in multiwall carbon nanotubes," Physical Review
Letters, vol. 95, no. 8, Article ID 086601, 4 pages, 2005.
[10] S. Haruehanroengra and W. Wang, "Analyzing conductance of mixed
carbon-nanotube bundles for interconnect applications," IEEE Electron
Device Letters, vol. 28, no. 8, pp. 756-759, 2007.
[11] M. Nihei, D. Kondo, A. Kawabata, et al., "Low-resistance multi-walled
carbon nanotube vias with parallel channel conduction of inner shells,"
in Proceedings of the IEEE International Interconnect Technology
Conference (IITC -05), pp. 234-236, June 2005.
[12] A. Naeemi and J. D. Meindl, "Compact physical models for multiwall
carbon-nanotube interconnects," IEEE Electron Device Letters, vol. 27,
no. 5, pp. 338-340, 2006.
[13] C. L. Cheung, A. Kurtz, H. Park, and C.M. Lieber, "Diametercontrolled
synthesis of carbon nanotubes," Journal of Physical Chemistry B, vol.
106, no. 10, pp. 2429-2433, 2002.
[14] A. Nieuwoudt and Y. Massoud, "On the optimal design, performance
and reliability of future carbon nanotub-based interconnect solutions,"
IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2097-2110,
2008.
[15] International Technology Roadmap for Semiconductors, 2005.
[16] B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and current
carrying capacity of carbon nanotubes," Applied Physics Letters, vol.
79, no. 8, pp. 1172-1174, 2001.
[17] http://www.nanohub.org/tools.
[18] http://www.eas.asu.edu/ptm/.
[19] N. Srivastava, R. V. Joshi, and K. Banerjee, "Carbon nanotube
interconnects: implications for performance, power dissipation and
thermal management," in Proceedings of IEEE International Electron
Devices Meeting (IEDM -05), pp. 249- 252,Washington, DC, USA,
2005.
[20] H. Li, et al., "Modeling of carbon nanotube interconnects and
comparative analysis with Cu interconnects," in Proceedings of
the Asia-Pacific Microwave Conference (APMC -06), 2006.
[21] Xilinx Corporation, Virtex-II 1.5V Field Programmable Gate Arrays
DS031-1, Version 2.5, April 2001.
[22] L. Shang. A. Kaviani. K. Balhala. "Dynamic Power Consumption in
Virtex-II FPGA Family", Proe. of IEEE Symp. On FPGAs, pp. 167-172
2002.
[23] S. N. Vijaykrishnan, A. Neuwodt, Y. Masood, "Predicting the
performance and reliability of future FPGAs routing architectures with
CNT interconnects"IET Circuit and device system 3(2) pp. 64-75,2009
[1] G. Lemieux and D. Lewis, Design of Interconnection Networks for
Programmable Logic, Kluwer Academic Publishers, 2004
[2] F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and
Characteristics of Field Programmable Gate Arrays," TCAD, vol. 24,
[3] A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison
between carbon nanotube and copper interconnects for gigascale
integration (GSI)", IEEE Electron Device Letters, vol. 26, pp. 84-86,
[4] A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison
between carbon nanotube and copper interconnects for gigascale
integration (GSI)," IEEE Electron Device Letters, vol. 26, no. 2, pp. 84-
86, 2005.
[5] N. Srivastava and K. Banerjee, "A comparative scaling analysis
of metallic and carbon nanotube interconnections for nanometer scale
VLSI technologies," in Proceedings of the 21st International VLSI
Multilevel Interconnection Conference (VMIC -04), pp. 393-398, 2004.
[6] A. Raychowdhury and K. Roy, "Modeling of metallic carbonnanotube
interconnects for circuit simulations and a comparison with Cu
interconnects for scaled technologies," IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no.
1, pp. 58-65, 2006.
[7] A. Raychowdhury and K. Roy, "A circuit model for carbon nanotube
interconnects: comparative study with Cu interconnects for scaled
technologies," in Proceedings of IEEE/ACM International Conference
on Computer-Aided Design (ICCAD -04), pp. 237-240, 2004.
[8] P. McEuen, M. Fuhrer, and H. Park, "Single-walled carbon nanotube
electronics," IEEE Transactions on Nanotechnology, vol. 1, no. 1, pp.
78-85, 2002.
[9] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, "Multichannel
ballistic transport in multiwall carbon nanotubes," Physical Review
Letters, vol. 95, no. 8, Article ID 086601, 4 pages, 2005.
[10] S. Haruehanroengra and W. Wang, "Analyzing conductance of mixed
carbon-nanotube bundles for interconnect applications," IEEE Electron
Device Letters, vol. 28, no. 8, pp. 756-759, 2007.
[11] M. Nihei, D. Kondo, A. Kawabata, et al., "Low-resistance multi-walled
carbon nanotube vias with parallel channel conduction of inner shells,"
in Proceedings of the IEEE International Interconnect Technology
Conference (IITC -05), pp. 234-236, June 2005.
[12] A. Naeemi and J. D. Meindl, "Compact physical models for multiwall
carbon-nanotube interconnects," IEEE Electron Device Letters, vol. 27,
no. 5, pp. 338-340, 2006.
[13] C. L. Cheung, A. Kurtz, H. Park, and C.M. Lieber, "Diametercontrolled
synthesis of carbon nanotubes," Journal of Physical Chemistry B, vol.
106, no. 10, pp. 2429-2433, 2002.
[14] A. Nieuwoudt and Y. Massoud, "On the optimal design, performance
and reliability of future carbon nanotub-based interconnect solutions,"
IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2097-2110,
2008.
[15] International Technology Roadmap for Semiconductors, 2005.
[16] B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and current
carrying capacity of carbon nanotubes," Applied Physics Letters, vol.
79, no. 8, pp. 1172-1174, 2001.
[17] http://www.nanohub.org/tools.
[18] http://www.eas.asu.edu/ptm/.
[19] N. Srivastava, R. V. Joshi, and K. Banerjee, "Carbon nanotube
interconnects: implications for performance, power dissipation and
thermal management," in Proceedings of IEEE International Electron
Devices Meeting (IEDM -05), pp. 249- 252,Washington, DC, USA,
2005.
[20] H. Li, et al., "Modeling of carbon nanotube interconnects and
comparative analysis with Cu interconnects," in Proceedings of
the Asia-Pacific Microwave Conference (APMC -06), 2006.
[21] Xilinx Corporation, Virtex-II 1.5V Field Programmable Gate Arrays
DS031-1, Version 2.5, April 2001.
[22] L. Shang. A. Kaviani. K. Balhala. "Dynamic Power Consumption in
Virtex-II FPGA Family", Proe. of IEEE Symp. On FPGAs, pp. 167-172
2002.
[23] S. N. Vijaykrishnan, A. Neuwodt, Y. Masood, "Predicting the
performance and reliability of future FPGAs routing architectures with
CNT interconnects"IET Circuit and device system 3(2) pp. 64-75,2009
@article{"International Journal of Electrical, Electronic and Communication Sciences:57244", author = "Kureshi Abdul Kadir and Mohd. Hasan", title = "Analysis of CNT Bundle and its Comparison with Copper for FPGAs Interconnects", abstract = "Each new semiconductor technology node
brings smaller transistors and wires. Although this makes
transistors faster, wires get slower. In nano-scale regime, the
standard copper (Cu) interconnect will become a major hurdle
for FPGA interconnect due to their high resistivity and
electromigration. This paper presents the comprehensive
evaluation of mixed CNT bundle interconnects and
investigates their prospects as energy efficient and high speed
interconnect for future FPGA routing architecture. All
HSPICE simulations are carried out at operating frequency of
1GHz and it is found that mixed CNT bundle implemented in
FPGAs as interconnect can potentially provide a substantial
delay and energy reduction over traditional interconnects at
32nm process technology.", keywords = "CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.", volume = "3", number = "9", pages = "1706-6", }
