A Virtual Simulation Environment for a Design and Verification of a GPGPU

When a small H/W IP is designed, we can develop an appropriate verification environment by observing the simulated signal waves, or using the serial test vectors for the fixed output. In the case of design and verification of a massive parallel processor with multiple IPs, it-s difficult to make a verification system with existing common verification environment, and to verify each partial IP. A TestDrive verification environment can build easy and reliable verification system that can produce highly intuitive results by applying Modelsim and SystemVerilog-s DPI. It shows many advantages, for example a high-level design of a GPGPU processor design can be migrate to FPGA board immediately.

Authors:

• Kwang Y. Lee
• Tae R. Park
• Jae C. Kwak
• Yong S. Koo

Keywords:

• Virtual Simulation
• Verification
• IP Design
• GPGPU

References:

[1] http://www.systemverilog.org
[2] http://www.doulos.com/knowhow/sysverilog/tutorial/dpi
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[4] GPGPU, General Purpose Computation Using Graphics Hardware,
http://www.gpgpu.org
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