A Novel Source/Drain-to-Gate Non-overlap MOSFET to Reduce Gate Leakage Current in Nano Regime
In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.
[1] C. -H. Choi, K. Y. Nam, Z. Yu, and R. W. Dutton, "Impact of gate
direct tunneling current on circuit performance: A simulation study,"
IEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec. 2001.
[2] International Technology Roadmap for Semiconductors, http:
//public.itrs.net/Files /2001 ITRS /Home.html.
[3] Y. Taur, "CMOS Design Near the Limits of Scaling," IBM J.R&D, vol.
46(2/3), pp. 213-222, Mar./May 2002.
[4] N. Sirisantana, Wei, L. and Roy, K. , "High Performance Low-Power
CMOS Circuits Using Multiple Channel Length and Multiple Oxide
Thickness," in Proc. of IEEE ICCD, pp. 227-232, Sept. 2000.
[5] F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control Gate
Leakage for sub 100nm CMOS," Proc. ISLPED, pp. 60-63, Aug. 2002.
[6] K. Roy, S. Mukhopadhyay, and H. M. Meimand, "Leakage Current
Mechanisms and Leakage Reduction Techniques in Deep-
Submicrometer CMOS Circuits," Proceedings of the IEEE, vol. 91,no. 2,
pp. 305-327, February 2003.
[7] D. Lee, D. Blaauw, and D. Sylvester ,"Analysis and Minimization
Techniques for Total Leakage Considering Gate Oxide Leakage," in
Proc. Of ACM/IEEE DAC, pp. 175-180, Jun. 2003.
[8] D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current
Analysis and Reduction for VLSI Circuits," IEEE Transactions on VLSI
Systems, vol. 12, no. 2, pp. 155-166, February 2004.
[9] A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, "Tradeoffs Between
Gate Oxide Leakage and Delay for Dual Tox Circuits," in Proceedings of
Design Automation Conference, 2004, pp. 761-766.
[10] N. Sirisantana and K. Roy;, "Low-power Design using Multiple Channel
Lengths and Oxide Thicknesses," IEEE Design & Test of Computers,
vol. 21, no. 1, pp. 56-63, Jan-Feb 2004.
[11] S. P. Mohanty and E. Kougianos. " Modeling and Reduction of Gate
Leakage during Behavioral Synthesis of Nano CMOS Circuits." In
Proceedings of the 19th IEEE International Conference on VLSI Design
(VLSID), 2006.
[12] Hyunjin Lee, Jongho Lee and Hyungcheol Shin, "DC and AC
Characteristics of Sub-50-nm MOSFETs with Source/Drain-to-Gate
Non-overlapped Structure." IEEE Transactions on Nanotechnology, vol.
1, No. 4, pp. 219-225, Dec 2002.
[13] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and
M. Bohr, "Scaling challenges and device design requirements for high
performance sub-50 nm gate length planar CMOS transistors," in Tech.
Dig. VLSI Sym., 2000, pp. 174-175.
[14] K. F. Schuegraf and C. Hu, "Hole injection SiO2 breakdown model for
very low voltage lifetime extrapolation," IEEE Transactions on Electron
Devices, Vol. 41, No. 5,pp 761-767, May 1994.
[15] W. -C. Lee and C. Hu, " Modeling CMOS tunneling currents through
ultrathin gate oxide due to conduction- and valence-band electron and
hole tunneling," IEEE Transactions on Electron Devices, Vol. 48, No. 7,
pp 1366-1373, July 2001.
[16] Fabien Pregaldiny, Christophe Lallement and Daniel Mathiot,
"Accounting for quantum mechanical effects from accumulation to
inversion, in a fully analytical surface potential-based MOSFET model,"
Solid-State Electronics, Vol.48, No. 5, pp.781-787, 2004.
[17] Taur, Y., and Ning, T.H.: ÔÇÿFundamentals of modern VLSI devices-
(Cambridge University Press, New York, 1998).
[18] Steve Shao-Shiun Chung and Tung-Chi Li, "An analytical thresholdvoltage
model of trench-isolated MOS devices with non-uniformly
doped substrates" IEEE Transactions On Electron Devices, Vol. 39, No.
3, pp 614-622,1992.
[19] ISE TCAD: Synopsys Santaurus Device simulator.
[1] C. -H. Choi, K. Y. Nam, Z. Yu, and R. W. Dutton, "Impact of gate
direct tunneling current on circuit performance: A simulation study,"
IEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec. 2001.
[2] International Technology Roadmap for Semiconductors, http:
//public.itrs.net/Files /2001 ITRS /Home.html.
[3] Y. Taur, "CMOS Design Near the Limits of Scaling," IBM J.R&D, vol.
46(2/3), pp. 213-222, Mar./May 2002.
[4] N. Sirisantana, Wei, L. and Roy, K. , "High Performance Low-Power
CMOS Circuits Using Multiple Channel Length and Multiple Oxide
Thickness," in Proc. of IEEE ICCD, pp. 227-232, Sept. 2000.
[5] F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control Gate
Leakage for sub 100nm CMOS," Proc. ISLPED, pp. 60-63, Aug. 2002.
[6] K. Roy, S. Mukhopadhyay, and H. M. Meimand, "Leakage Current
Mechanisms and Leakage Reduction Techniques in Deep-
Submicrometer CMOS Circuits," Proceedings of the IEEE, vol. 91,no. 2,
pp. 305-327, February 2003.
[7] D. Lee, D. Blaauw, and D. Sylvester ,"Analysis and Minimization
Techniques for Total Leakage Considering Gate Oxide Leakage," in
Proc. Of ACM/IEEE DAC, pp. 175-180, Jun. 2003.
[8] D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current
Analysis and Reduction for VLSI Circuits," IEEE Transactions on VLSI
Systems, vol. 12, no. 2, pp. 155-166, February 2004.
[9] A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, "Tradeoffs Between
Gate Oxide Leakage and Delay for Dual Tox Circuits," in Proceedings of
Design Automation Conference, 2004, pp. 761-766.
[10] N. Sirisantana and K. Roy;, "Low-power Design using Multiple Channel
Lengths and Oxide Thicknesses," IEEE Design & Test of Computers,
vol. 21, no. 1, pp. 56-63, Jan-Feb 2004.
[11] S. P. Mohanty and E. Kougianos. " Modeling and Reduction of Gate
Leakage during Behavioral Synthesis of Nano CMOS Circuits." In
Proceedings of the 19th IEEE International Conference on VLSI Design
(VLSID), 2006.
[12] Hyunjin Lee, Jongho Lee and Hyungcheol Shin, "DC and AC
Characteristics of Sub-50-nm MOSFETs with Source/Drain-to-Gate
Non-overlapped Structure." IEEE Transactions on Nanotechnology, vol.
1, No. 4, pp. 219-225, Dec 2002.
[13] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and
M. Bohr, "Scaling challenges and device design requirements for high
performance sub-50 nm gate length planar CMOS transistors," in Tech.
Dig. VLSI Sym., 2000, pp. 174-175.
[14] K. F. Schuegraf and C. Hu, "Hole injection SiO2 breakdown model for
very low voltage lifetime extrapolation," IEEE Transactions on Electron
Devices, Vol. 41, No. 5,pp 761-767, May 1994.
[15] W. -C. Lee and C. Hu, " Modeling CMOS tunneling currents through
ultrathin gate oxide due to conduction- and valence-band electron and
hole tunneling," IEEE Transactions on Electron Devices, Vol. 48, No. 7,
pp 1366-1373, July 2001.
[16] Fabien Pregaldiny, Christophe Lallement and Daniel Mathiot,
"Accounting for quantum mechanical effects from accumulation to
inversion, in a fully analytical surface potential-based MOSFET model,"
Solid-State Electronics, Vol.48, No. 5, pp.781-787, 2004.
[17] Taur, Y., and Ning, T.H.: ÔÇÿFundamentals of modern VLSI devices-
(Cambridge University Press, New York, 1998).
[18] Steve Shao-Shiun Chung and Tung-Chi Li, "An analytical thresholdvoltage
model of trench-isolated MOS devices with non-uniformly
doped substrates" IEEE Transactions On Electron Devices, Vol. 39, No.
3, pp 614-622,1992.
[19] ISE TCAD: Synopsys Santaurus Device simulator.
@article{"International Journal of Information, Control and Computer Sciences:52430", author = "Ashwani K. Rana and Narottam Chand and Vinod Kapoor", title = "A Novel Source/Drain-to-Gate Non-overlap MOSFET to Reduce Gate Leakage Current in Nano Regime", abstract = "In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.", keywords = "Gate tunneling current, analytical model, spacer
dielectrics, DIBL, subthreshold slope.", volume = "5", number = "10", pages = "1102-7", }
