Scholarly

Mathematical Modelling of Single Phase Unity Power Factor Boost Converter

Year: 2009 Volume: 3 Issue: 6 1418 - 1421 Pages

Abstract: An optimal control strategy based on simple model, a single phase unity power factor boost converter is presented with an evaluation of first order differential equations. This paper presents an evaluation of single phase boost converter having power factor correction. The simple discrete model of boost converter is formed and optimal control is obtained, digital PI is adopted to adjust control error. The method of instantaneous current control is proposed in this paper for its good tracking performance of dynamic response. The simulation and experimental results verified our design.

A Ring Segmented Bus Architecture for Globally Asynchronous Locally Synchronous System

Year: 2009 Volume: 3 Issue: 6 1412 - 1417 Pages

Abstract: Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several architectures have been proposed as bus architectures for a GALS system : shared bus, segmented bus, ring bus, and so on. In this study, we propose a ring segmented bus architecture which is a combination of segmented bus and ring bus architecture with the aim of throughput enhancement. In a segmented bus architecture, segments are connected in series. By connecting the segments at the end of the bus and constructing the ring bus, it becomes possible to allocate a channel of the bus bidirectionally. The bus channel is allocated to the shortest path between segments. We consider a metastable operation caused by asynchronous communication between segments and a burst transfer between segments. According to the result of simulation, it is shown that the GALS system designed by the proposed method has the desired operations.

Secret Communications Using Synchronized Sixth-Order Chuas's Circuits

Year: 2009 Volume: 3 Issue: 6 1406 - 1411 Pages

Abstract: In this paper, we use Generalized Hamiltonian systems approach to synchronize a modified sixth-order Chua's circuit, which generates hyperchaotic dynamics. Synchronization is obtained between the master and slave dynamics with the slave being given by an observer. We apply this approach to transmit private information (analog and binary), while the encoding remains potentially secure.

Compensation Method Eliminating Voltage Distortions in PWM Inverter

Year: 2009 Volume: 3 Issue: 6 1398 - 1405 Pages

Abstract: The switching lag-time and the voltage drop across the power devices cause serious waveform distortions and fundamental voltage drop in pulse width-modulated inverter output. These phenomenons are conspicuous when both the output frequency and voltage are low. To estimate the output voltage from the PWM reference signal it is essential to take account of these imperfections and to correct them. In this paper, on-line compensation method is presented. It needs three simple blocs to add at the ideal reference voltages. This method does not require any additional hardware circuit and off- line experimental measurement. The paper includes experimental results to demonstrate the validity of the proposed method. It is applied, finally, in case of indirect vector controlled induction machine and implemented using dSpace card.

MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems

Year: 2009 Volume: 3 Issue: 6 1392 - 1397 Pages

Abstract: The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.

On the Analysis of Bandwidth Management for Hybrid Load Balancing Scheme in WLANs

Year: 2009 Volume: 3 Issue: 6 1387 - 1391 Pages

Abstract: In wireless networks, bandwidth is scare resource and it is essential to utilize it effectively. This paper analyses effects of using different bandwidth management techniques on the network performances of the Wireless Local Area Networks (WLANs) that use hybrid load balancing scheme. In particular, we study three bandwidth management schemes, namely Complete Sharing (CS), Complete Partitioning (CP), and Partial Sharing (PS). Performances of these schemes are evaluated by simulation experiments in term of percentage of network association blocking. Our results show that the CS scheme can provide relatively low blocking percentage in various network traffic scenarios whereas the PS scheme can enhance quality of services of the multimedia traffic with rather small expenses on the blocking percentage of the best effort traffic.

Transformer Diagnosis Based on Coupled Circuits Method Modelling

Year: 2009 Volume: 3 Issue: 6 1382 - 1386 Pages

Abstract: Diagnostic goal of transformers in service is to detect the winding or the core in fault. Transformers are valuable equipment which makes a major contribution to the supply security of a power system. Consequently, it is of great importance to minimize the frequency and duration of unwanted outages of power transformers. So, Frequency Response Analysis (FRA) is found to be a useful tool for reliable detection of incipient mechanical fault in a transformer, by finding winding or core defects. The authors propose as first part of this article, the coupled circuits method, because, it gives most possible exhaustive modelling of transformers. And as second part of this work, the application of FRA in low frequency in order to improve and simplify the response reading. This study can be useful as a base data for the other transformers of the same categories intended for distribution grid.

A SAW-less Dual-Band CDMA Diversity and Simultaneous-GPS Zero-IF Receiver

Year: 2009 Volume: 3 Issue: 6 1378 - 1381 Pages

Abstract: We present a dual-band (Cellular & PCS) dual-path zero-IF receiver for CDMA2000 diversity, monitoring and simultaneous-GPS. The secondary path is a SAW-less diversity CDMA receiver which can be also used for advanced features like monitoring when supported with an additional external VCO. A GPS receiver is integrated with its dedicated VCO allowing simultaneous positioning during a cellular call. The circuit is implemented in a 0.25μm 40GHz-fT BiCMOS process and uses a HVQFN 56-pin package. It consumes a maximum 300mW from a 2.8V supply in dual-modes. The chip area is 12.8mm2.

Optimal Compensation of Reactive Power in the Restructured Distribution Network

Year: 2009 Volume: 3 Issue: 6 1374 - 1377 Pages

Abstract: In this paper optimal capacitor placement problem has been formulated in a restructured distribution network. In this scenario the distribution network operator can consider reactive energy also as a service that can be sold to transmission system. Thus search for optimal location, size and number of capacitor banks with the objective of loss reduction, maximum income from selling reactive energy to transmission system and return on investment for capacitors, has been performed. Results is influenced with economic value of reactive energy, therefore problem has been solved for various amounts of it. The implemented optimization technique is genetic algorithm. For any value of reactive power economic value, when reverse of investment index increase and change from zero or negative values to positive values, the threshold value of selling reactive power has been obtained. This increasing price of economic parameter is reasonable until the network losses is less than loss before compensation.

Optimal Allocation of FACTS Devices for ATC Enhancement Using Bees Algorithm

Year: 2009 Volume: 3 Issue: 6 1366 - 1373 Pages

Abstract: In this paper, a novel method using Bees Algorithm is proposed to determine the optimal allocation of FACTS devices for maximizing the Available Transfer Capability (ATC) of power transactions between source and sink areas in the deregulated power system. The algorithm simultaneously searches the FACTS location, FACTS parameters and FACTS types. Two types of FACTS are simulated in this study namely Thyristor Controlled Series Compensator (TCSC) and Static Var Compensator (SVC). A Repeated Power Flow with FACTS devices including ATC is used to evaluate the feasible ATC value within real and reactive power generation limits, line thermal limits, voltage limits and FACTS operation limits. An IEEE30 bus system is used to demonstrate the effectiveness of the algorithm as an optimization tool to enhance ATC. A Genetic Algorithm technique is used for validation purposes. The results clearly indicate that the introduction of FACTS devices in a right combination of location and parameters could enhance ATC and Bees Algorithm can be efficiently used for this kind of nonlinear integer optimization.

Keywords:
ATC
Bees Algorithm
TCSC
SVC

Effect of Flaying Capacitors on Improving the 4 Level Three-Cell Inverter

Year: 2009 Volume: 3 Issue: 6 1361 - 1365 Pages

Abstract: With the rapid advanced of technology, the industrial processes become increasingly demanding, from the point of view, power quality and controllability. The advent of multi levels inverters responds partially to these requirements. But actually, the new generation of multi-cells inverters permits to reach more performances, since, it offers more voltage levels. The disadvantage in the increase of voltage levels by the number of cells in cascades is on account of series igbts synchronisation loss, from where, a limitation of cells in cascade to 4. Regarding to these constraints, a new topology is proposed in this paper, which increases the voltage levels of the three-cell inverter from 4 to 8; with the same number of igbts, and using less stored energy in the flaying capacitors. The details of operation and modelling of this new inverter structure are also presented, then tested thanks to a three phase induction motor. KeywordsFlaying capacitors, Multi-cells inverter, pwm, switchers, modelling.

Devising and Assessing the Efficacy of Mobile-Assisted Instructional Modes in Mobile Learning

Year: 2009 Volume: 3 Issue: 6 1356 - 1360 Pages

Abstract: The assessment of the efficacy of devised Mobile- Assisted Instructional Modes in Mobile Learning was the focus of this research. The study adopted pre-test, post-test, control group quasi-experimental design. Research instruments were developed, validated and used for collecting data. Findings revealed that the students exposed to Mobile Task Based Learning Mode (MTBLM) in using Mobile-Assisted Instruction (MAI) performed significantly better. The implication of these findings is that, the Audio tutorial and Practice Mode (ATPM) (Stimulus instruments) of MAI had been found better over the other modes used in the study.

A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number

Year: 2009 Volume: 3 Issue: 6 1349 - 1355 Pages

Abstract: This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiply-accumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

A Case Study on Appearance Based Feature Extraction Techniques and Their Susceptibility to Image Degradations for the Task of Face Recognition

Year: 2009 Volume: 3 Issue: 6 1340 - 1348 Pages

Abstract: Over the past decades, automatic face recognition has become a highly active research area, mainly due to the countless application possibilities in both the private as well as the public sector. Numerous algorithms have been proposed in the literature to cope with the problem of face recognition, nevertheless, a group of methods commonly referred to as appearance based have emerged as the dominant solution to the face recognition problem. Many comparative studies concerned with the performance of appearance based methods have already been presented in the literature, not rarely with inconclusive and often with contradictory results. No consent has been reached within the scientific community regarding the relative ranking of the efficiency of appearance based methods for the face recognition task, let alone regarding their susceptibility to appearance changes induced by various environmental factors. To tackle these open issues, this paper assess the performance of the three dominant appearance based methods: principal component analysis, linear discriminant analysis and independent component analysis, and compares them on equal footing (i.e., with the same preprocessing procedure, with optimized parameters for the best possible performance, etc.) in face verification experiments on the publicly available XM2VTS database. In addition to the comparative analysis on the XM2VTS database, ten degraded versions of the database are also employed in the experiments to evaluate the susceptibility of the appearance based methods on various image degradations which can occur in "real-life" operating conditions. Our experimental results suggest that linear discriminant analysis ensures the most consistent verification rates across the tested databases.

Neural Network Ensemble-based Solar Power Generation Short-Term Forecasting

Year: 2009 Volume: 3 Issue: 6 1334 - 1339 Pages

Abstract: This paper presents the applicability of artificial neural networks for 24 hour ahead solar power generation forecasting of a 20 kW photovoltaic system, the developed forecasting is suitable for a reliable Microgrid energy management. In total four neural networks were proposed, namely: multi-layred perceptron, radial basis function, recurrent and a neural network ensemble consisting in ensemble of bagged networks. Forecasting reliability of the proposed neural networks was carried out in terms forecasting error performance basing on statistical and graphical methods. The experimental results showed that all the proposed networks achieved an acceptable forecasting accuracy. In term of comparison the neural network ensemble gives the highest precision forecasting comparing to the conventional networks. In fact, each network of the ensemble over-fits to some extent and leads to a diversity which enhances the noise tolerance and the forecasting generalization performance comparing to the conventional networks.

Fast Search for MPEG Video Clips Using Adjacent Pixel Intensity Difference Quantization Histogram Feature

Year: 2009 Volume: 3 Issue: 6 1330 - 1333 Pages

Abstract: In this paper, we propose a novel fast search algorithm for short MPEG video clips from video database. This algorithm is based on the adjacent pixel intensity difference quantization (APIDQ) algorithm, which had been reliably applied to human face recognition previously. An APIDQ histogram is utilized as the feature vector of the frame image. Instead of fully decompressed video frames, partially decoded data, namely DC images are utilized. Combined with active search [4], a temporal pruning algorithm, fast and robust video search can be realized. The proposed search algorithm has been evaluated by 6 hours of video to search for given 200 MPEG video clips which each length is 15 seconds. Experimental results show the proposed algorithm can detect the similar video clip in merely 80ms, and Equal Error Rate (ERR) of 3 % is achieved, which is more accurately and robust than conventional fast video search algorithm.

Keywords:
Fast search
adjacent pixel intensity difference quantization (APIDQ)
DC image
histogram feature.

Design of Variable Fractional-Delay FIR Differentiators

Year: 2009 Volume: 3 Issue: 6 1325 - 1329 Pages

Abstract: In this paper, the least-squares design of variable fractional-delay (VFD) finite impulse response (FIR) digital differentiators is proposed. The used transfer function is formulated so that Farrow structure can be applied to realize the designed system. Also, the symmetric characteristics of filter coefficients are derived, which leads to the complexity reduction by saving almost a half of the number of coefficients. Moreover, all the elements of related vectors or matrices for the optimal process can be represented in closed forms, which make the design easier. Design example is also presented to illustrate the effectiveness of the proposed method.

High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure

Year: 2009 Volume: 3 Issue: 6 1319 - 1324 Pages

Abstract: In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.

Mounting Time Reduction using Content-Based Block Management for NAND Flash File System

Year: 2009 Volume: 3 Issue: 6 1315 - 1318 Pages

Abstract: The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. The YAFFS, one of the NAND flash file system, is widely used in the embedded device. However, the existing YAFFS takes long time to mount the file system because it scans whole spare areas in all pages of NAND flash memory. In order to solve this problem, we propose a new content-based flash file system using a mounting time reduction technique. The proposed method only scans partial spare areas of some special pages by using content-based block management. The experimental results show that the proposed method reduces the average mounting time by 87.2% comparing with JFFS2 and 69.9% comparing with YAFFS.

Photonic Crystals for Novel Applications in Integrated-Optic Communication Systems and Devices

Year: 2009 Volume: 3 Issue: 6 1310 - 1314 Pages

Abstract: Photonic Crystal (PhC) based devices are being increasingly used in multifunctional, compact devices in integrated optical communication systems. They provide excellent controllability of light, yet maintaining the small size required for miniaturization. In this paper, the band gap properties of PhCs and their typical applications in optical waveguiding are considered. Novel PhC based applications such as nonlinear switching and tapers are considered and simulation results are shown using the accurate time-domain numerical method based on Finite Difference Time Domain (FDTD) scheme. The suitability of these devices for novel applications is discussed and evaluated.

International Journal of Electrical, Electronic and Communication Sciences

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