Formation of Protective Silicide-Aluminide Coating on Gamma-TiAl Advanced Material

In this study, the Si-aluminide coating was prepared on gamma-TiAl [Ti-45Al-2Nb-2Mn-1B (at. %)] via liquid-phase slurry procedure. The high temperature oxidation resistance of this diffusion coating was evaluated at 1100 °C for 400 hours. The results of the isothermal oxidation showed that the formation of Si-aluminide coating can remarkably improve the high temperature oxidation of bare gamma-TiAl alloy. The identification of oxide scale microstructure showed that the formation of protective Al2O3+SiO2 mixed oxide scale along with a continuous, compact and uniform layer of Ti5Si3 beneath the surface oxide scale can act as an oxygen diffusion barrier during the high temperature oxidation. The other possible mechanisms related to the formation of Si-aluminide coating and oxide scales were also discussed.

Preparation of CuAlO2 Thin Films on Si or Sapphire Substrate by Sol-Gel Method Using Metal Acetate or Nitrate

CuAlO2 thin films are prepared on Si or sapphire substrate by sol-gel method using two kinds of sols. One is combination of Cu acetate and Al acetate basic, and the other is Cu nitrate and Al nitrate. In the case of acetate sol, XRD peaks of CuAlO2 observed at annealing temperature of 800-950 ºC on both Si and sapphire substrates. In contrast, in the case of the films prepared using nitrate on Si substrate, XRD peaks of CuAlO2 have been observed only at the annealing temperature of 800-850 ºC. At annealing temperature of 850ºC, peaks of other species have been observed beside the CuAlO2 peaks, then, the CuAlO2 peaks disappeared at annealing temperature of 900 °C with increasing in intensity of the other peaks. Intensity of the other peaks decreased at annealing temperature of 950 ºC with appearance of broad SiO2 peak. In the present, we ascribe these peaks as metal silicide.

Ni Metallization on SiGe Nanowire

The mechanism of nickel (Ni) metallization in silicon-germanium (Si0.5Ge0.5) alloy nanowire (NW) was studied. Transmission electron microscope imaging with in-situ annealing was conducted at temperatures of 200oC to 600°C. During rapid formation of Ni germanosilicide, loss of material from from the SiGe NW occurred which led to the formation of a thin Ni germanosilicide filament and eventual void. Energy dispersive X-ray spectroscopy analysis along the SiGe NW before and after annealing determined that Ge atoms tend to out-diffuse from the Ni germanosilicide towards the Ni source in the course of annealing. A model for the Ni germanosilicide formation in SiGe NW is proposed to explain this observation.

Switching Behaviors of HfO2/NiSix Based RRAM

This paper presents a study of Ni-silicides as the bottom electrode of HfO2-based RRAM. Various silicidation conditions were used to obtain different Ni concentrations within the Ni-silicide bottom electrode, namely Ni2Si, NiSi, and NiSi2. A 10nm HfO2 switching material and 50nm TiN top electrode was then deposited and etched into 500nm by 500nm square RRAM cells. Cell performance of the Ni2Si and NiSi cells were good, while the NiSi2 cell could not switch reliably, indicating that the presence of Ni in the bottom electrode is important for good switching.

Measurement of I-V Characteristics of a PtSi/p-Si Schottky Barrier Diode at low Temperatures

The current-voltage characteristics of a PtSi/p-Si Schottky barrier diode was measured at the temperature of 85 K and from the forward bias region of the I-V curve, the electrical parameters of the diode were measured by three methods. The results obtained from the two methods which considered the series resistance were in close agreement with each other and from them barrier height (), ideality factor (n) and series resistance () were found to be 0.2045 eV, 2.877 and 14.556 K respectively. By measuring the I-V characteristics in the temperature range of 85-136 K the electrical parameters were observed to have strong dependency on temperature. The increase of barrier height and decrease of ideality factor with increasing temperature is attributed to the existence of barrier height inhomogeneities in the silicide-semiconductor structure.

Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate

This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Silicon-Waveguide Based Silicide Schottky- Barrier Infrared Detector for on-Chip Applications

We prove detailed analysis of a waveguide-based Schottky barrier photodetector (SBPD) where a thin silicide film is put on the top of a silicon-on-insulator (SOI) channel waveguide to absorb light propagating along the waveguide. Taking both the confinement factor of light absorption and the wall scanning induced gain of the photoexcited carriers into account, an optimized silicide thickness is extracted to maximize the effective gain, thereby the responsivity. For typical lengths of the thin silicide film (10-20 Ðçm), the optimized thickness is estimated to be in the range of 1-2 nm, and only about 50-80% light power is absorbed to reach the maximum responsivity. Resonant waveguide-based SBPDs are proposed, which consist of a microloop, microdisc, or microring waveguide structure to allow light multiply propagating along the circular Si waveguide beneath the thin silicide film. Simulation results suggest that such resonant waveguide-based SBPDs have much higher repsonsivity at the resonant wavelengths as compared to the straight waveguidebased detectors. Some experimental results about Si waveguide-based SBPD are also reported.

Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Photoluminescence Properties of β-FeSi2 on Cu- or Au-coated Si

The photoluminescence (PL) at 1.55 μm from semiconducting β-FeSi2 has attracted a noticeable interest for silicon-based optoelectronic applications. Moreover, its high optical absorption coefficient (higher than 105 cm-1 above 1.0 eV) allows this semiconducting material to be used as photovoltanics devices. A clear PL spectrum for β-FeSi2 was observed by Cu or Au coating on Si(001). High-crystal-quality β-FeSi2 with a low-level nonradiative center was formed on a Cu- or Au- reated Si layer. This method of deposition can be applied to other materials requiring high crystal quality.