Abstract: Radio Frequency Identification (RFID) is a blooming technology which uses radio frequency to track the objects. This technology transmits signals between tag and reader to fetch information from the tag with a unique serial identity. Generally, the drawbacks of RFID technology are high cost, high consumption of power and weak authentication systems between a reader and a tag. The proposed protocol utilizes less dynamic power using reversible truncated multipliers which are implemented in RFID tag-reader with mutual authentication protocol system to reduce both leakage and dynamic power consumption. The proposed system was simulated using Xilinx and Cadence tools.
Abstract: Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.
Abstract: This paper impart the design and testing of
Nanotechnology based sequential circuits using multiplexer
conservative QCA (MX-CQCA) logic gates, which is easily testable
using only two vectors. This method has great prospective in the
design of sequential circuits based on reversible conservative logic
gates and also smashes the sequential circuits implemented in
traditional gates in terms of testability. Reversible circuits are similar
to usual logic circuits except that they are built from reversible gates.
Designs of multiplexer conservative QCA logic based two vectors
testable double edge triggered (DET) sequential circuits in VHDL
language are also accessible here; it will also diminish intricacy in
testing side. Also other types of sequential circuits such as D, SR, JK
latches are designed using this MX-CQCA logic gate. The objective
behind the proposed design methodologies is to amalgamate
arithmetic and logic functional units optimizing key metrics such as
garbage outputs, delay, area and power. The projected MX-CQCA
gate outshines other reversible gates in terms of the intricacy, delay.
Abstract: Reversible logic is becoming more and more prominent
as the technology sets higher demands on heat, power, scaling
and stability. Reversible gates are able at any time to "undo" the
current step or function. Multiple-valued logic has the advantage of
transporting and evaluating higher bits each clock cycle than binary.
Moreover, we demonstrate in this paper, combining these disciplines
we can construct powerful multiple-valued reversible logic structures.
In this paper a reversible block implemented by pseudo floatinggate
can perform AD-function and a DA-function as its reverse
application.