Abstract: Dynamic Voltage and Frequency Scaling (DVFS)
multicore platforms are promising execution platforms that enable
high computational performance, less energy consumption and
flexibility in scheduling the system processes. However, the
resulting interleaving and memory interference together with per-core
frequency tuning make real-time guarantees hard to be delivered.
Besides, energy consumption represents a strong constraint for the
deployment of such systems on energy-limited settings. Identifying
the system configurations that would achieve a high performance and
consume less energy while guaranteeing the system schedulability is
a complex task in the design of modern embedded systems. This work
studies the trade-off between energy consumption, cores utilization
and memory bottleneck and their impact on the schedulability of
DVFS multicore time-critical systems with a hierarchy of shared
memories. We build a model-based framework using Parametrized
Timed Automata of UPPAAL to analyze the mutual impact of
performance, energy consumption and schedulability of DVFS
multicore systems, and demonstrate the trade-off on an actual case
study.
Abstract: Even though past, current and future trends suggest that multicore and cloud computing systems are increasingly prevalent/ubiquitous, this class of parallel systems is nonetheless underutilized, in general, and barely used for research on employing parallel Delaunay triangulation for parallel surface modeling and generation, in particular. The performances, of actual/physical and virtual/cloud multicore systems/machines, at executing various algorithms, which implement various parallelization strategies of the incremental insertion technique of the Delaunay triangulation algorithm, were evaluated. T-tests were run on the data collected, in order to determine whether various performance metrics differences (including execution time, speedup and efficiency) were statistically significant. Results show that the actual machine is approximately twice faster than the virtual machine at executing the same programs for the various parallelization strategies. Results, which furnish the scalability behaviors of the various parallelization strategies, also show that some of the differences between the performances of these systems, during different runs of the algorithms on the systems, were statistically significant. A few pseudo superlinear speedup results, which were computed from the raw data collected, are not true superlinear speedup values. These pseudo superlinear speedup values, which arise as a result of one way of computing speedups, disappear and give way to asymmetric speedups, which are the accurate kind of speedups that occur in the experiments performed.
Abstract: This paper introduces novel approaches to partitioning
and mapping in terms of model-based embedded multicore system
engineering and further discusses benefits, industrial relevance and
features in common with existing approaches. In order to assess
and evaluate results, both approaches have been applied to a real
industrial application as well as to various prototypical demonstrative
applications, that have been developed and implemented for
different purposes. Evaluations show, that such applications improve
significantly according to performance, energy efficiency, meeting
timing constraints and covering maintaining issues by using
the AMALTHEA platform and the implemented approaches.
Furthermore, the model-based design provides an open, expandable,
platform independent and scalable exchange format between
OEMs, suppliers and developers on different levels. Our proposed
mechanisms provide meaningful multicore system utilization since
load balancing by means of partitioning and mapping is effectively
performed with regard to the modeled systems including hardware,
software, operating system, scheduling, constraints, configuration and
more data.